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AgeCommit message (Expand)AuthorFilesLines
2013-11-28Remove "high 16" register class macros for xmm/ymm/zmmH. Peter Anvin1-9/+3
2013-11-27opflags: Separate vector registers into low-16 and high-16Jin Kyu Song1-4/+23
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-1/+4
2013-08-29AVX-512: Add OPMASK instructionsJin Kyu Song1-1/+3
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-3/+3
2013-08-06AVX-512: Add support for parsing bracesJin Kyu Song1-6/+15
2013-07-19BR 3392260: Handle instructions only separated by vector SIB sizeH. Peter Anvin1-0/+2
2013-03-04Drop SAME_AS flag from instruction matcherBen Rudiak-Gould1-3/+0
2013-03-03insns: Remove pushseg/popseg internal bytecodesBen Rudiak-Gould1-4/+10
2013-03-01Remove +sBen Rudiak-Gould1-11/+6
2012-09-16opflags: Rework opflags bits with OP_ macrosCyrill Gorcunov1-163/+163
2012-09-16opflags: Introduce opflags generating macrosCyrill Gorcunov1-0/+4
2012-09-16opflags: Drop never used REG_RIP/REG_EIPCyrill Gorcunov1-3/+0
2012-09-10opflags: Extend opflags_t to 64 bitsCyrill Gorcunov1-84/+84
2011-08-28Add IS_SREG and IS_FSGS helpersCyrill Gorcunov1-0/+3
2010-08-24Optimize mov r64,immH. Peter Anvin1-7/+8
2009-10-13opflags: more int32_t -> opflags_t conversionsH. Peter Anvin1-0/+239
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