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| author | Ben Rudiak-Gould <benrudiak@gmail.com> | 2013-03-03 18:43:07 +0400 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2013-03-03 20:50:46 +0400 |
| commit | d1ac29a3cc513642a8d42ddf964b903f5e1508d4 (patch) | |
| tree | 7c582f2c8fb9f48f13bc74ee96ca4631286f37fb /opflags.h | |
| parent | 83e6924e1a583d432e9a54c68a59779da5d8ce3d (diff) | |
| download | nasm-d1ac29a3cc513642a8d42ddf964b903f5e1508d4.tar.gz nasm-d1ac29a3cc513642a8d42ddf964b903f5e1508d4.tar.bz2 nasm-d1ac29a3cc513642a8d42ddf964b903f5e1508d4.zip | |
insns: Remove pushseg/popseg internal bytecodes
This patch is getting rid of the following bytecodes
'pushseg','popseg','pushseg2','popseg2' and simplifies
overall code.
[gorcunov@: a few style fixes]
Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Diffstat (limited to 'opflags.h')
| -rw-r--r-- | opflags.h | 14 |
1 files changed, 10 insertions, 4 deletions
@@ -191,10 +191,16 @@ typedef uint64_t opflags_t; #define REG_DREG (GEN_SUBCLASS(2) | REG_CLASS_CDT | BITS32 | REGISTER) /* DRn */ #define REG_TREG (GEN_SUBCLASS(3) | REG_CLASS_CDT | BITS32 | REGISTER) /* TRn */ #define REG_SREG ( REG_CLASS_SREG | BITS16 | REGISTER) /* any segment register */ -#define REG_CS (GEN_SUBCLASS(1) | REG_CLASS_SREG | BITS16 | REGISTER) /* CS */ -#define REG_DESS (GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* DS, ES, SS */ -#define REG_FSGS (GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS, GS */ -#define REG_SEG67 (GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* Unimplemented segment registers */ + +/* Segment registers */ +#define REG_ES (GEN_SUBCLASS(0) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* ES */ +#define REG_CS (GEN_SUBCLASS(1) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* CS */ +#define REG_SS (GEN_SUBCLASS(0) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* SS */ +#define REG_DS (GEN_SUBCLASS(1) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* DS */ +#define REG_FS (GEN_SUBCLASS(0) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS */ +#define REG_GS (GEN_SUBCLASS(1) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* GS */ +#define REG_FSGS ( GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS or GS */ +#define REG_SEG67 ( GEN_SUBCLASS(5) | REG_CLASS_SREG | BITS16 | REGISTER) /* Unimplemented segment registers */ /* Special GPRs */ #define REG_SMASK SUBCLASS_MASK /* a mask for the following */ |