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path: root/target-ppc/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt1-1/+0
2016-09-07ppc: Provide basic raise_exception_* functionsBenjamin Herrenschmidt1-0/+8
2016-09-07target-ppc: Introduce POWER ISA 3.0 flagNikunj A Dadhania1-1/+4
2016-08-10ppc: Introduce a function to look up CPU alias stringsThomas Huth1-0/+1
2016-07-12target-*: Clean up cpu.h header guardsMarkus Armbruster1-3/+4
2016-07-05ppc/hash64: Add proper real mode translation supportBenjamin Herrenschmidt1-0/+2
2016-07-01ppc: Update LPCR definitionsBenjamin Herrenschmidt1-3/+13
2016-06-29target-*: Don't redefine cpu_exec()Peter Crosthwaite1-2/+0
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt1-1/+16
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt1-1/+3
2016-06-23ppc: Fix POWER7 and POWER8 exception definitionsBenjamin Herrenschmidt1-1/+10
2016-06-14ppc: Improve PCR bit selection in ppc_set_compat()Thomas Huth1-0/+2
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth1-0/+1
2016-06-07Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell1-2/+0
2016-06-07virtio: move bi-endian target support to a single locationGreg Kurz1-2/+0
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt1-1/+1
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt1-0/+4
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt1-0/+2
2016-05-30ppc: Use split I/D mmu modes to avoid flushes on interruptsBenjamin Herrenschmidt1-3/+8
2016-05-30ppc: Remove MMU_MODEn_SUFFIX definitionsBenjamin Herrenschmidt1-3/+0
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-2/+0
2016-05-19target-ppc: make cpu-qom.h not target specificPaolo Bonzini1-113/+52
2016-05-12tb: consistently use uint32_t for tb->flagsEmilio G. Cota1-1/+1
2016-04-18ppc: Fix the range check in the LSWI instructionThomas Huth1-0/+10
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater1-0/+10
2016-03-24ppc: A couple more dummy POWER8 Book4 regsBenjamin Herrenschmidt1-0/+3
2016-03-24ppc: Add dummy CIABR SPRBenjamin Herrenschmidt1-0/+1
2016-03-24ppc: Add POWER8 IAMR registerBenjamin Herrenschmidt1-0/+1
2016-03-24ppc: Add dummy SPR_IC for POWER8Benjamin Herrenschmidt1-0/+1
2016-03-24ppc: Create cpu_ppc_set_papr() helperBenjamin Herrenschmidt1-0/+1
2016-03-24ppc: Update SPR definitionsBenjamin Herrenschmidt1-7/+47
2016-03-16ppc: Add a few more P8 PMU SPRsBenjamin Herrenschmidt1-0/+7
2016-03-16ppc: Define the PSPB register on POWER8Thomas Huth1-0/+1
2016-02-23all: Clean up includesPeter Maydell1-1/+0
2016-02-01target-ppc: mcrfs should always update FEX/VX and only clear exception bitsJames Clarke1-0/+6
2016-01-30target-ppc: Make every FPSCR_ macro have a corresponding FP_ macroJames Clarke1-9/+22
2016-01-30target-ppc: Rework SLB page size lookupDavid Gibson1-0/+1
2016-01-30target-ppc: rename and export maybe_bswap_register()Greg Kurz1-0/+1
2016-01-30ppc: Clean up error handling in ppc_set_compat()David Gibson1-1/+1
2015-11-30target-ppc: Move the FPSCR bit update macros to cpu.hMadhavan Srinivasan1-0/+21
2015-11-11ppc: Add/Re-introduce MMU model definitions needed by PR KVMBharata B Rao1-0/+6
2015-10-23ppc/spapr: Add "ibm,pa-features" property to the device-treeBenjamin Herrenschmidt1-0/+1
2015-10-23ppc: Add mmu_model defines for arch 2.03 and 2.07Benjamin Herrenschmidt1-5/+5
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson1-1/+0
2015-09-25ppc: Rename ELF_MACHINE to be PPC specificPeter Crosthwaite1-2/+2
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-1/+1
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite1-1/+1
2015-04-28Convert (ffs(val) - 1) to ctz32(val)Stefan Hajnoczi1-2/+2
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-8/+1
2015-03-09PPC: Introduce the Virtual Time Base (VTB) SPR registerCyril Bur1-0/+1
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