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2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini5-22/+50
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+0
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson9-16/+10
2014-05-27target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2-1/+6
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2-1/+22
2014-05-27target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias1-1/+1
2014-05-27target-arm: A64: Generalize update_spsel for the various ELsEdgar E. Iglesias1-5/+6
2014-05-27target-arm: A64: Generalize ERET to various ELsEdgar E. Iglesias1-5/+6
2014-05-27target-arm: A64: Trap ERET from EL0 at translation timeEdgar E. Iglesias1-0/+4
2014-05-27target-arm: A64: Forbid ERET to higher or unimplemented ELsEdgar E. Iglesias1-2/+6
2014-05-27target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Add a feature flag for EL3Edgar E. Iglesias1-0/+1
2014-05-27target-arm: Add a feature flag for EL2Edgar E. Iglesias1-0/+1
2014-05-27target-arm: A64: Introduce aarch64_banked_spsr_index()Edgar E. Iglesias3-2/+17
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias4-6/+12
2014-05-27target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias2-4/+4
2014-05-27target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias2-4/+4
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias3-5/+5
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias3-8/+8
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias6-10/+11
2014-05-27target-arm: Use a 1:1 mapping between EL and MMU indexEdgar E. Iglesias2-9/+5
2014-05-27target-arm: A32: Use get_mem_index for load/storesEdgar E. Iglesias1-106/+106
2014-05-27target-arm/translate.c: Use get_mem_index() for SRS memory accessesPeter Maydell1-2/+2
2014-05-27target-arm/translate.c: Clean up mmu index handling for ldrt/strtPeter Maydell1-12/+17
2014-05-27target-arm: Move get_mem_index to translate.hEdgar E. Iglesias2-9/+9
2014-05-27target-arm: implement CPACR register logic for ARMv7Fabian Aggeler1-4/+28
2014-05-27target-arm: Fix segfault on startup when KVM enabledChristoffer Dall1-1/+1
2014-05-15Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513'...Peter Maydell2-5/+7
2014-05-13target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell1-0/+7
2014-05-13savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela1-5/+0
2014-05-13kvm: reset state from the CPU's reset methodPaolo Bonzini4-4/+17
2014-05-05vmstate: s/VMSTATE_INT32_LE/VMSTATE_INT32_POSITIVE_LE/Michael S. Tsirkin1-1/+1
2014-05-01target-arm: Correct a comment refering to EL0Edgar E. Iglesias1-1/+1
2014-05-01target-arm: A64: Fix a typo when declaring TLBI opsEdgar E. Iglesias1-12/+12
2014-05-01target-arm: A64: Handle blr lrEdgar E. Iglesias1-1/+2
2014-05-01target-arm: Make vbar_write 64bit friendly on 32bit hostsEdgar E. Iglesias1-1/+1
2014-05-01target-arm: implement WFE/YIELD as a yield for AArch64Rob Herring1-0/+6
2014-05-01target-arm: Implement XScale cache lockdown operations as NOPsPeter Maydell1-0/+15
2014-04-17target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée1-1/+1
2014-04-17arm: translate.c: Fix smlald InstructionPeter Crosthwaite1-11/+23
2014-04-17target-arm/gdbstub64.c: remove useless 'break' statement.Chen Gang1-2/+0
2014-04-17target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell4-3/+13
2014-04-17target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pcPeter Maydell1-4/+8
2014-04-17target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell1-1/+1
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell5-9/+42
2014-04-17target-arm: Implement Cortex-A57 implementation-defined system registersPeter Maydell1-0/+55
2014-04-17target-arm: Implement RVBAR registerPeter Maydell3-0/+16
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell2-31/+25
2014-04-17target-arm: Implement auxiliary fault status registersPeter Maydell1-0/+9
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