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path: root/target-arm/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2014-06-09target-arm: VFPv4 implies half-precision extensionPeter Maydell1-2/+1
2014-06-09target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell1-4/+4
2014-06-09target-arm: Remove unnecessary setting of feature bitsPeter Maydell1-2/+0
2014-06-09target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell1-3/+0
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell1-0/+1
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel1-0/+2
2014-05-27target-arm: Fix segfault on startup when KVM enabledChristoffer Dall1-1/+1
2014-05-13kvm: reset state from the CPU's reset methodPaolo Bonzini1-0/+7
2014-04-17target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell1-1/+1
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell1-2/+6
2014-04-17target-arm: Implement RVBAR registerPeter Maydell1-0/+9
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell1-0/+1
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring1-1/+1
2014-04-17target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell1-0/+7
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell1-0/+1
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-1/+1
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber1-1/+3
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-0/+7
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton1-0/+1
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell1-4/+4
2014-02-26target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell1-2/+2
2014-02-26target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell1-0/+2
2014-02-26target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell1-1/+1
2014-02-20target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell1-4/+2
2014-02-20target-arm: Define names for SCTLR bitsPeter Maydell1-1/+1
2014-01-31ARM: Convert MIDR to a propertyAlistair Francis1-0/+1
2014-01-14Merge remote branch 'luiz/queue/qmp' into qmpqEdgar E. Iglesias1-5/+2
2014-01-14target-arm: Switch ARMCPUInfo arrays to use terminator entriesPeter Maydell1-3/+6
2014-01-06hw: Remove assert_no_error usagesPeter Crosthwaite1-5/+2
2013-12-17target-arm: Clean up handling of AArch64 PSTATEPeter Maydell1-0/+6
2013-12-17ARM: arm_cpu_reset: make it possible to use high vectors for reset_excAntony Pavlov1-0/+5
2013-12-17ARM: cpu: add "reset_hivecs" propertyAntony Pavlov1-0/+13
2013-12-17target-arm/cpu: Convert reset CBAR to a propertyPeter Crosthwaite1-0/+17
2013-12-17target-arm: Define and use ARM_FEATURE_CBARPeter Crosthwaite1-9/+3
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel1-0/+1
2013-12-10target-arm: Don't hardcode KVM target CPU to be A15Peter Maydell1-0/+2
2013-12-10target-arm: Allow secondary KVM CPUs to be booted via PSCIPeter Maydell1-0/+7
2013-12-10target-arm: Add ARMCPU field for Linux device-tree 'compatible' stringPeter Maydell1-0/+50
2013-09-10target-arm: Prepare translation for AArch64 codeAlexander Graf1-0/+8
2013-09-10target-arm: Disable 32 bit CPUs in 64 bit linux-user buildsPeter Maydell1-2/+7
2013-09-10target-arm: fix ARMv7M stack alignment on resetSebastian Ottlik1-1/+1
2013-09-10target-arm: Make '-cpu any' available in linux-user mode onlyPeter Maydell1-0/+4
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-2/+2
2013-08-20target-arm: Implement the generic timerPeter Maydell1-0/+7
2013-08-20target-arm: Make IRQ and FIQ gpio lines on the CPU objectPeter Maydell1-0/+60
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-1/+3
2013-07-27cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XMLAndreas Färber1-0/+1
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber1-0/+2
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber1-0/+1
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