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| author | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:30 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:30 +0000 |
| commit | d356312fdc8640af929e0dbab61c6e514d47feb8 (patch) | |
| tree | ef3cdeaf3ef2e87cb21cc42199f2fe5188f82ae9 /target-arm/cpu.c | |
| parent | b197ebd410f0298ec078c3048f9cfb9f6bfc3b3c (diff) | |
| download | qemu-d356312fdc8640af929e0dbab61c6e514d47feb8.tar.gz qemu-d356312fdc8640af929e0dbab61c6e514d47feb8.tar.bz2 qemu-d356312fdc8640af929e0dbab61c6e514d47feb8.zip | |
target-arm: Clean up handling of AArch64 PSTATE
The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However it's convenient
for QEMU to use it to hold the various PSTATE architectural bits
in the same format the architecture specifies for SPSR registers
(since this is the same format the kernel uses for signal handlers
and the KVM register). Add some structure to how we deal with it:
* document what env->pstate is
* add some #defines for various bits in it
* add helpers for reading/writing it taking account of caching
of NZCV, and use them where appropriate
* reset it on startup
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1385645602-18662-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8288c7db39..408d207865 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -89,6 +89,12 @@ static void arm_cpu_reset(CPUState *s) if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ env->aarch64 = 1; +#if defined(CONFIG_USER_ONLY) + env->pstate = PSTATE_MODE_EL0t; +#else + env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F + | PSTATE_MODE_EL1h; +#endif } #if defined(CONFIG_USER_ONLY) |