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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-07 15:39:12 +0000 |
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| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-07 15:39:12 +0000 |
| commit | 24e207c33b46fc006bc64f074eea66dd8fab1a56 (patch) | |
| tree | a930d1f0449f91069b518147d2ba61b982a37321 /target-mips | |
| parent | eb88d2d050e24f0ca6683f6246c717a398bd9578 (diff) | |
| download | qemu-24e207c33b46fc006bc64f074eea66dd8fab1a56.tar.gz qemu-24e207c33b46fc006bc64f074eea66dd8fab1a56.tar.bz2 qemu-24e207c33b46fc006bc64f074eea66dd8fab1a56.zip | |
Mention missing CPU save/restore.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4381 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/TODO | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/TODO b/target-mips/TODO index dda580118d..c58956cff6 100644 --- a/target-mips/TODO +++ b/target-mips/TODO @@ -29,6 +29,7 @@ General To cope with these differences, Qemu currently flushes the TLB at each ASID change. Using the MMU modes to implement ASIDs hinges on implementing the global bit efficiently. +- save/restore of the CPU state is not implemented (see machine.c). MIPS64 ------ |