From 24e207c33b46fc006bc64f074eea66dd8fab1a56 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Wed, 7 May 2008 15:39:12 +0000
Subject: Mention missing CPU save/restore.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4381 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-mips/TODO | 1 +
 1 file changed, 1 insertion(+)

(limited to 'target-mips')

diff --git a/target-mips/TODO b/target-mips/TODO
index dda580118d..c58956cff6 100644
--- a/target-mips/TODO
+++ b/target-mips/TODO
@@ -29,6 +29,7 @@ General
   To cope with these differences, Qemu currently flushes the TLB at
   each ASID change. Using the MMU modes to implement ASIDs hinges on
   implementing the global bit efficiently.
+- save/restore of the CPU state is not implemented (see machine.c).
 
 MIPS64
 ------
-- 
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