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| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-11-30 15:39:54 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-11-30 16:18:28 +0100 |
| commit | be116bf2875060bacc2f95416157f9ab9e95c520 (patch) | |
| tree | cc8b275ae0455e4589fba5bb0a8d98b46eebe82c /target-mips/translate.c | |
| parent | c5947020cab4d920ac810200379f04b88d5514d7 (diff) | |
| download | qemu-be116bf2875060bacc2f95416157f9ab9e95c520.tar.gz qemu-be116bf2875060bacc2f95416157f9ab9e95c520.tar.bz2 qemu-be116bf2875060bacc2f95416157f9ab9e95c520.zip | |
target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in both
user and system mode. Use the physical address insteead in system
mode.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 41 |
1 files changed, 13 insertions, 28 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index e9d92249ef..9d62b64b51 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -912,16 +912,24 @@ OP_ST(sd,st64); #endif #undef OP_ST +#ifdef CONFIG_USER_ONLY #define OP_LD_ATOMIC(insn,fname) \ static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ { \ TCGv t0 = tcg_temp_new(); \ tcg_gen_mov_tl(t0, arg1); \ tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \ tcg_temp_free(t0); \ } +#else +#define OP_LD_ATOMIC(insn,fname) \ +static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ +{ \ + gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \ +} +#endif OP_LD_ATOMIC(ll,ld32s); #if defined(TARGET_MIPS64) OP_LD_ATOMIC(lld,ld64); @@ -941,7 +949,7 @@ static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ct tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ generate_exception(ctx, EXCP_AdES); \ gen_set_label(l1); \ - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \ tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \ @@ -957,34 +965,11 @@ static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ct static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ { \ TCGv t0 = tcg_temp_new(); \ - TCGv t1 = tcg_temp_new(); \ - int l1 = gen_new_label(); \ - int l2 = gen_new_label(); \ - int l3 = gen_new_label(); \ - \ - tcg_gen_andi_tl(t0, arg2, almask); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \ - tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ - generate_exception(ctx, EXCP_AdES); \ - gen_set_label(l1); \ - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ - tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \ - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, llval)); \ - tcg_gen_qemu_##ldname(t1, arg2, ctx->mem_idx); \ - tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l2); \ - tcg_temp_free(t1); \ - tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \ - tcg_gen_movi_tl(t0, 1); \ - gen_store_gpr(t0, rt); \ - tcg_gen_br(l3); \ - gen_set_label(l2); \ - tcg_gen_movi_tl(t0, 0); \ + gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \ gen_store_gpr(t0, rt); \ - gen_set_label(l3); \ tcg_temp_free(t0); \ } #endif - OP_ST_ATOMIC(sc,st32,ld32s,0x3); #if defined(TARGET_MIPS64) OP_ST_ATOMIC(scd,st64,ld64,0x7); @@ -1137,7 +1122,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, opn = "swr"; break; case OPC_LL: - save_cpu_state(ctx, 0); + save_cpu_state(ctx, 1); op_ldst_ll(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "ll"; @@ -1179,7 +1164,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, break; #endif case OPC_SC: - save_cpu_state(ctx, 0); + save_cpu_state(ctx, 1); op_ldst_sc(t1, t0, rt, ctx); opn = "sc"; break; |