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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-29 18:29:05 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-29 18:29:05 +0000 |
| commit | 01cbcb25e11e0d31d498bf00cadb4d71e32a1cc2 (patch) | |
| tree | fe48f7f2ce8669638a75339730c04b6e18a6f804 /target-mips/translate.c | |
| parent | 6f5676e3eca4ac8362e3dbbca4226bc43284320b (diff) | |
| download | qemu-01cbcb25e11e0d31d498bf00cadb4d71e32a1cc2.tar.gz qemu-01cbcb25e11e0d31d498bf00cadb4d71e32a1cc2.tar.bz2 qemu-01cbcb25e11e0d31d498bf00cadb4d71e32a1cc2.zip | |
Avoid qemu SIGFPE for MIPS DIV, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4621 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index d6239a5f57..8290220440 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1902,21 +1902,17 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1); { - TCGv r_tmp1 = new_tmp(); - TCGv r_tmp2 = new_tmp(); - TCGv r_tmp3 = new_tmp(); + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); - tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]); - tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]); - tcg_gen_div_i32(r_tmp3, r_tmp1, r_tmp2); - tcg_gen_rem_i32(r_tmp1, r_tmp1, r_tmp2); - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp3); - tcg_gen_ext_i32_tl(cpu_T[1], r_tmp1); - gen_store_LO(cpu_T[0], 0); - gen_store_HI(cpu_T[1], 0); - dead_tmp(r_tmp1); - dead_tmp(r_tmp2); - dead_tmp(r_tmp3); + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); + tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]); + tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]); + tcg_gen_ext32s_tl(r_tmp1, r_tmp1); + tcg_gen_ext32s_tl(r_tmp2, r_tmp2); + gen_store_LO(r_tmp1, 0); + gen_store_HI(r_tmp2, 0); } gen_set_label(l1); } |