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2013-11-24iflag: Start using new instruction flags engineCyrill Gorcunov1-116/+2
Here we start using instruction flags generator. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-11-20PREFETCHWT1: Add a new instruction flagJin Kyu Song1-0/+1
PREFETCHWT1 instruction's CPUID was TBD before. Now it has its new CPUID bit : PREFETCHWT1 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song1-0/+1
As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving the content of bound register. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20iflags: Use UINT64_C() for 64bit valuesJin Kyu Song1-79/+79
UINT64_C() macro is used for iflags as it becomes 64bit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20SHA: Add SHA instructionsJin Kyu Song1-0/+1
New instruction extensions of SHA family are added. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20MPX: Add MPX instructionsJin Kyu Song1-0/+1
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-11-20disasm: add support for emitting split EA formatH. Peter Anvin1-0/+1
Add support for emitting split EA format in the disassembler, indicated by the MIB instruction flag. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
2013-09-14AVX-512: Added AVX-512PF instructionsJin Kyu Song1-0/+1
Added Prefetch (AVX-512PF) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1. CPUID feature flag for PREFETCHWT1 is TBD but PREFETCHWT1 is included in this commit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-14AVX-512: Add AVX-512ER instructionsJin Kyu Song1-2/+3
Added Exponential and Reciprocal (AVX-512ER) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1. IF_AVX512 is now shared by all AVX-512* instructions as a bit mask. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-09-14AVX-512: Add AVX-512CD instructionsJin Kyu Song1-0/+1
Added Conflict Detection (AVX-512CD) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-29AVX-512: Add IF_SPMASK and fix IF_PFMASKJin Kyu Song1-1/+2
Defined IF_SPMASK for specific processor types and fixed IF_PFMASK to mask the exact preferred bits only. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-28AVX-512: Change the data type for instruction flagsJin Kyu Song1-25/+28
Increased the size of data type for instruction flags from 32bits to 64bits. And a new type (iflags_t) is defined for better maintainability. Bigger data type is needed because more instruction set types are coming but there were not enough space for them. Since they are not bit masks, only one instruction set is allowed for each instruction. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-08-16AVX-512: Add EVEX encoding and new instructionsJin Kyu Song1-3/+7
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2013-05-10Add IF_TBM flagCyrill Gorcunov1-0/+1
For TMB instructions Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2012-02-25HLE: Change NOHLE to be an instruction flagH. Peter Anvin1-22/+24
The way our matching system works we have to make NOHLE an instruction flag rather than an byte code; by the time we run the byte code interpreter we have already picked an instruction pattern once and for all. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-25Add support for warning on invalid LOCK prefixesH. Peter Anvin1-0/+1
Add an LOCK flag to the instruction template, and make the presence of a LOCK prefix trigger a warning if it is not set. Simplify the LOCK and HLE logic by hard-coding the knowledge that operand 0 has to be memory. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2012-02-09insns: Add AVX2 transactional synchronization extensionsCyrill Gorcunov1-0/+2
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-07-17Some cleanup on insns.hCyrill Gorcunov1-75/+78
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-07-08A few more AVX2 spec instructionsH. Peter Anvin1-0/+1
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-07insns.h: Add BMI1 and BMI2 flags for further usageJasper Neuman1-0/+2
Signed-off-by: Jasper Neuman <jasper.neumann@web.de> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2011-06-25Add IF_AVX2 flagCyrill Gorcunov1-0/+1
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
2010-08-24assemble: add an OPT instruction flags for optimizing assembly onlyH. Peter Anvin1-1/+2
Add an OPT flag to only use a pattern for optimizing assembly only. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-08-19ndisasm: handle VEX.LIGH. Peter Anvin1-1/+1
A lot of instructions ignore the L bit in the VEX prefix, just like a lot of instructions ignore the W bit, so don't use them in the sub-table select. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2009-07-25Enable fuzzy matching of operand sizesH. Peter Anvin1-11/+14
This allows automatic fuzzy matching of operand sizes. If an operand size is not specified, but there is exactly one possible size for the instruction, select that instruction size. This requires a second pass through the instruction patterns, and so is slightly slower, but should be a lot easier to get right than the S- flags, and works even when there is more than one instruction. The new SX (Size eXact) flag can be used to prevent fuzzy matching completely. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-05-03Use lower case for VEX and XOP in instructions tableH. Peter Anvin1-1/+1
Use lower case for VEX and XOP ("vex", "xop") to avoid visual confusion (and in the future potential real confusion) with upper-case hexadecimal numbers. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-05-03Infrastructure support for AMD's new XOP prefixH. Peter Anvin1-1/+1
Handle AMD's XOP prefixes; they use basically the same encoding as VEX prefixes, so treat them simply as a variant of VEX. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-02-21FMA instructions won't be in Sandy BridgeH. Peter Anvin1-0/+1
The FMA instructions aren't scheduled for Sandy Bridge after all. They will be "in a future processor", so create a placeholder for now.
2008-05-23AVX FMA: Instruction table for the AVX FMA instructionsH. Peter Anvin1-1/+2
This adds the AVX FMA instructions to the instruction table, which should complete the AVX work.
2008-05-21Disassembler: select table based on VEX prefixesH. Peter Anvin1-0/+1
We can use the new VEX prefixes to select into a large table of new opcode spaces. Since the table is (currently) sparse, add logic so we don't end up producing tons of empty tables for no good reason. This is also necessary since VEX is likely to reuse opcode bytes that would appear as prefixes at some point, which would cause conflicts with the regular tables.
2008-05-20Add DY, YWORD, and the SY instruction flagH. Peter Anvin1-1/+2
Add the DY instruction, YWORD keyword, and an SY marker for instruction sizes. Add a few more AVX sample instructions.
2008-05-13Make insnsb.c an actual compilation unitH. Peter Anvin1-0/+3
"make alldeps" doesn't really like it when included files end in *.c. Instead of renaming insnsb.c to insnsb.h, make it an actual compilation unit, since there really isn't any reason for it not to be.
2008-05-12Generate a byte array instead of using strings for the byte codesH. Peter Anvin1-1/+1
Generate a byte array instead of using C compiler strings for the byte codes. This has a few advantages: - No need to special-case zero due to broken C compilers. - Only insns.pl only ever reads the string, so we can invent our own syntax. - Compaction. - We can give it the proper, unsigned type.
2008-05-06Actually spell "Sandy Bridge" correctlyH. Peter Anvin1-1/+1
2008-05-06Sandy Bridge, not Sandy Banks; add WestmereH. Peter Anvin1-1/+2
2008-05-04First cut at AVX machinery.H. Peter Anvin1-0/+2
First cut at AVX machinery support. The only instruction implemented is VPERMIL2PS, and it's probably buggy. I'm checking this in with the hope that other people can start helping out with (a) testing this, and (b) adding instructions. NDISASM support is not there yet.
2008-04-04Correctly identify SBYTE in the optimizerH. Peter Anvin1-1/+3
Correctly identify SBYTE in the optimizer, *HOWEVER*, this change will cause nuisance warnings to be issued; that will have to be fixed.
2007-12-29regularized spelling of license to match name of LICENSE fileBeroset1-1/+1
2007-09-24Support __float*__ for floating-point numbers in expressionsH. Peter Anvin1-7/+1
Add special operators to allow the use of floating-point constants in contexts other than DW/DD/DQ/DT/DO. As part of this checkin, make MAX_KEYWORD generated by tokhash.pl, since it knows what all the keywords are so it can tell which one is the longest.
2007-09-22Add the AMD SSE4a and LZCNT instructionsH. Peter Anvin1-2/+3
Add AMD SSE4a and LZCNT
2007-09-18Support generating NaNs and infinitiesH. Peter Anvin1-2/+2
Support generating NaNs and infinities as part of floating-point constants.
2007-09-18Speed up the disassembler by allowing prefixed instruction tablesH. Peter Anvin1-1/+10
Modify the disassembler so that we can have separate instruction tables for prefixed instructions. As it was, all instructions which started with 0F were linearly searched, and that is by now more than half the instruction set.
2007-09-18Implement "oword" (128 bits) as a first-class sizeH. Peter Anvin1-0/+1
Implement oword, reso, do, as well as the SO flag to instructions. No instructions are actually flagged with SO yet, but this allows us to specify 128-bit sizes in instruction patterns.
2007-09-17Actually generate SSE5 instructionsH. Peter Anvin1-1/+2
This checkin completes what is required to actually generate SSE5 instructions. No support in the disassembler yet. This checkin covers: - Support for actually generating DREX prefixes. - Support for matching operand "operand X must match Y"
2007-09-17Initial support for four arguments per instructionH. Peter Anvin1-8/+10
For SSE5, we will need to support four arguments per instruction.
2007-09-12Add (untested!) SSSE3, SSE4.1, SSE4.2 instructionsH. Peter Anvin1-0/+1
Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the previous \332 flag changed to \335). This is necessary to get the REX prefix in the right place for instructions that use it. We are going to have to go in and change existing instruction patterns which use these, as well.
2007-09-12Remove $Id$ tags (useless with git)H. Peter Anvin1-1/+0
Remove CVS $Id$ tags, since git doesn't use them.
2007-09-12Macros for SSSE3/SSE4 instruction setsH. Peter Anvin1-0/+3
Add instruction set flags for the SSSE3, SSE4.1 and SSE4.2 instruction subsets.
2007-09-11Make the big instruction arrays "const"H. Peter Anvin1-0/+4
Make the big instruction arrays "const", so they end up in readonly storage. While we're at it, move their prototypes into insns.h.
2007-09-10Use an actual enum for the opcodeH. Peter Anvin1-5/+5
Use an actual named enum for the opcode, that way it shows up in cleartext while debugging.
2007-04-17Handle "LOCK as REX.R" for MOV CRx; fix warning for invalid 64-bit regsH. Peter Anvin1-3/+5
- MOV gpr,CRx or MOV CRx,gpr can access high control registers with a LOCK prefix; handle that in both the assembler and disassembler. - Get a saner error message when trying to access high resources in non-64-bit mode.
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