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2010-03-25BR2975768: Update AMD LWP instructions to match upcoming changesCyrill Gorcunov1-8/+9
2010-01-06insns.dat: in 64-bit mode, accept "monitor rax,ecx,edx".H. Peter Anvin1-0/+1
2010-01-03BR2924380: Add AMD LWP instructionsCyrill Gorcunov1-0/+20
2010-01-03BR2924383: fix XOP instructionsCyrill Gorcunov1-4/+10
2010-01-03BR2924583: fix FMA4 instructionsCyrill Gorcunov1-2/+2
2009-12-16insns.dat: Restore default size of memory operandsCyrill Gorcunov1-22/+22
2009-12-03insns.dat: AVX -- no need for IF_ARx in templateCyrill Gorcunov1-12/+12
2009-11-09insns.dat: remove non-DREX SSE5 instructionsH. Peter Anvin1-31/+0
2009-11-09SSE5: remove all DREX-based instructionsH. Peter Anvin1-275/+1
2009-11-06MOVD xmmreg: not valid with REX.WH. Peter Anvin1-4/+4
2009-11-03IMUL: sbyteX fix -- last oneCyrill Gorcunov1-3/+3
2009-11-03IMUL: fix an additional incorrect sbyte useH. Peter Anvin1-1/+1
2009-11-03BR 2887108: fix incorrect sbyte usage in IMULH. Peter Anvin1-2/+2
2009-08-07insns.dat -- convert FMA instructionsCyrill Gorcunov1-192/+192
2009-08-07insns.dat -- convert AVX instructions part2Cyrill Gorcunov1-347/+347
2009-08-07insns.dat -- convert AVX instructions part1Cyrill Gorcunov1-281/+281
2009-07-27insns.dat: operand-size syntax for XOP instructionsCyrill Gorcunov1-18/+18
2009-07-27insns.dat -- operand-size syntax for XOP instructionsCyrill Gorcunov1-150/+150
2009-06-28Add copyright notice to insns.datH. Peter Anvin1-6/+35
2009-06-26ndisasm: fix disassembly of JRCXZH. Peter Anvin1-1/+1
2009-06-26insns.dat: reformatH. Peter Anvin1-104/+104
2009-06-26insns.dat: add relaxed forms for XOP/FMA4/CVT16 instructionsH. Peter Anvin1-146/+148
2009-06-24insns: make the MMX version of PINSRW match the SSE/AVX onesH. Peter Anvin1-3/+3
2009-06-24Intel FMA: drop relaxed formsH. Peter Anvin1-192/+192
2009-06-24Fix the PINSR series of instructionsH. Peter Anvin1-18/+21
2009-06-24insns.dat: fix typos: VCMPORD_SP[SD] entered as VCMPORS_SP[SD]H. Peter Anvin1-4/+2
2009-06-24insns.dat: collapse relaxed formsH. Peter Anvin1-1212/+608
2009-05-17insns.dat - fixup for XOP (SSE5) AMD instructionsCyrill Gorcunov1-13/+23
2009-05-15insns.dat - introcuce base XOP (SSE5) AMD instructionsCyrill Gorcunov1-0/+199
2009-03-17BR 2690688: Fix opcodes for FMA instructionsH. Peter Anvin1-264/+264
2009-03-17BR 2690688: add missing VFM instructionsH. Peter Anvin1-24/+168
2009-03-16BR 2689316: PEXTRQ requires REX.WH. Peter Anvin1-1/+1
2009-03-16insns.dat: fix VFNM instructions incorrectly spelled as VFMNH. Peter Anvin1-48/+48
2009-02-23Add VPCLMUL instructionsH. Peter Anvin1-0/+12
2009-02-21PCLMUL is apparently targeted for Westmere with the AES stuffH. Peter Anvin1-6/+5
2009-02-21BR 2557903: fix disassembly of a set of SSE MOV* instructionsH. Peter Anvin1-6/+6
2009-02-21BR 2541252: Fix issues in insns.dat, mostly related to LZCNT and POPCNTH. Peter Anvin1-10/+10
2009-02-21BR 2592476: Treat WAIT as a prefix even though it's really an instructionH. Peter Anvin1-11/+10
2009-02-21Fix opcode for VADDSUBPS; operands for VBLEND; add SSE for AES opsH. Peter Anvin1-14/+14
2009-02-21FMA instructions won't be in Sandy BridgeH. Peter Anvin1-241/+240
2009-02-18Update the VFMA* instructions per the AVX spec version 5H. Peter Anvin1-64/+240
2009-02-18insns.dat: fix minor formatting anomaliesH. Peter Anvin1-3/+3
2008-12-29BR 2413278: Nonoptimal forms of arithmetic instructions involving AXH. Peter Anvin1-0/+24
2008-11-06The POPCNT instruction does not need sizes on memory operandsH. Peter Anvin1-3/+3
2008-11-06BR 2229703: POPCNT r64,rm64 not POPCNT r64,rm32H. Peter Anvin1-1/+1
2008-10-23The CRC32 instructions can take 66 prefixes as well as F2H. Peter Anvin1-5/+5
2008-10-23BR 2190521: fix the CRC32 opcodesH. Peter Anvin1-5/+5
2008-10-22BR 2187210: Fix PFRCPV and PFRSQRTVH. Peter Anvin1-2/+2
2008-10-08Reshuffle and move the bytecodes for segment register push/popH. Peter Anvin1-5/+5
2008-10-07Add missing IMUL pattern: reg64,imm8H. Peter Anvin1-0/+1
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