Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2016-09-21 | Support Lower to reserve internal register(s) different from targetReg. | sivarv | 1 | -17/+30 |
2016-08-19 | Implement the proposed design for RyuJIT's LIR. (#6689) | Pat Gavlin | 1 | -0/+2 |
2016-08-11 | Reformat jit sources with clang-tidy and format | Michelle McDaniel | 1 | -48/+54 |
2016-08-01 | Replace the LSRA stack with a hash table. | Pat Gavlin | 1 | -4/+16 |
2016-07-01 | Consider spilled lcl var as contained memory operands for codegen purpose. | sivarv | 1 | -1/+3 |
2016-05-04 | Multi-reg call node support. | sivarv | 1 | -1/+1 |
2016-01-27 | Update license headers | dotnet-bot | 1 | -4/+3 |
2015-01-30 | Initial commit to populate CoreCLR repo | dotnet-bot | 1 | -0/+140 |