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| author | sivarv <sivarv@microsoft.com> | 2016-07-01 11:41:02 -0700 |
|---|---|---|
| committer | sivarv <sivarv@microsoft.com> | 2016-07-01 17:01:32 -0700 |
| commit | d92b629cdb742c42ef7b6a35f3ba55104539c9bd (patch) | |
| tree | f8c6027189dd7db635e34878bff7bbf8dafcddea /src/jit/nodeinfo.h | |
| parent | 652f1f081416c1ecbc06a29e5448f4fef7e0a4f4 (diff) | |
| download | coreclr-d92b629cdb742c42ef7b6a35f3ba55104539c9bd.tar.gz coreclr-d92b629cdb742c42ef7b6a35f3ba55104539c9bd.tar.bz2 coreclr-d92b629cdb742c42ef7b6a35f3ba55104539c9bd.zip | |
Consider spilled lcl var as contained memory operands for codegen purpose.
Diffstat (limited to 'src/jit/nodeinfo.h')
| -rw-r--r-- | src/jit/nodeinfo.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/jit/nodeinfo.h b/src/jit/nodeinfo.h index 5b6fab87ea..8fc48f9150 100644 --- a/src/jit/nodeinfo.h +++ b/src/jit/nodeinfo.h @@ -31,6 +31,7 @@ public: isDelayFree = false; hasDelayFreeSrc = false; isTgtPref = false; + regOptional = false; } // dst @@ -119,7 +120,8 @@ public: // isTgtPref is set to true when we have a rmw op, where we would like the result to be allocated // in the same register as op1. unsigned char isTgtPref:1; - + // Whether a spilled second src can be treated as a contained operand + unsigned char regOptional:1; public: |