blob: c6334ca27fb3db63c192b7a927e980a89f0da42c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*/
#ifndef __CACHE_H
#define __CACHE_H
/*
* Structure for the cache controller
*/
struct cache_info {
phys_addr_t base; /* Base physical address of cache device. */
};
struct cache_ops {
/**
* get_info() - Get basic cache info
*
* @dev: Device to check (UCLASS_CACHE)
* @info: Place to put info
* @return 0 if OK, -ve on error
*/
int (*get_info)(struct udevice *dev, struct cache_info *info);
};
#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
/**
* cache_get_info() - Get information about a cache controller
*
* @dev: Device to check (UCLASS_CACHE)
* @info: Returns cache info
* @return 0 if OK, -ve on error
*/
int cache_get_info(struct udevice *dev, struct cache_info *info);
#endif
|
