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| author | Dinh Nguyen <dinguyen@kernel.org> | 2019-04-23 16:55:03 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-05 08:48:50 -0400 |
| commit | 84b124db3584d8b3f1a42c1506983323bce9983f (patch) | |
| tree | b343ae85d7c2600aca0edd911b4b01c6975ac4ad /include/cache.h | |
| parent | 2bac27ce945e8399ea2c1404310ead450c065819 (diff) | |
| download | u-boot-84b124db3584d8b3f1a42c1506983323bce9983f.tar.gz u-boot-84b124db3584d8b3f1a42c1506983323bce9983f.tar.bz2 u-boot-84b124db3584d8b3f1a42c1506983323bce9983f.zip | |
dm: cache: Create a uclass for cache
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.
Add a uclass and a test for cache.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'include/cache.h')
| -rw-r--r-- | include/cache.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/include/cache.h b/include/cache.h new file mode 100644 index 0000000000..c6334ca27f --- /dev/null +++ b/include/cache.h @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef __CACHE_H +#define __CACHE_H + +/* + * Structure for the cache controller + */ +struct cache_info { + phys_addr_t base; /* Base physical address of cache device. */ +}; + +struct cache_ops { + /** + * get_info() - Get basic cache info + * + * @dev: Device to check (UCLASS_CACHE) + * @info: Place to put info + * @return 0 if OK, -ve on error + */ + int (*get_info)(struct udevice *dev, struct cache_info *info); +}; + +#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops) + +/** + * cache_get_info() - Get information about a cache controller + * + * @dev: Device to check (UCLASS_CACHE) + * @info: Returns cache info + * @return 0 if OK, -ve on error + */ +int cache_get_info(struct udevice *dev, struct cache_info *info); + +#endif |