summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass14-0/+14
2020-05-18common: Drop log.h from common headerSimon Glass3-0/+3
2020-03-30clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2Marek Vasut1-1/+2
2019-08-09clk: renesas: Add R8A77980 V3H clock tablesMarek Vasut3-0/+262
2019-04-09clk: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut8-130/+215
2019-04-09clk: renesas: Synchronize Gen2 tables with Linux 5.0Marek Vasut4-16/+14
2019-04-09clk: renesas: Add R8A77965 clock tablesMarek Vasut4-19/+346
2019-03-25clk: renesas: Add support for setting MMCIF clock divider on Gen2Marek Vasut1-0/+42
2019-03-25clk: renesas: Fix swapped div and mul in debug output on Gen2Marek Vasut1-1/+1
2019-03-25clk: renesas: Fix SDH clock divider decoding on Gen2Marek Vasut1-5/+9
2019-02-25clk: rmobile: Drop def_bool per SoCMarek Vasut1-10/+0
2018-12-03clk: renesas: Allow reconfiguring SDHI clock on Gen3Marek Vasut1-7/+3
2018-06-14clk: rmobile: Add R8A77995 RPC clockMarek Vasut1-0/+5
2018-06-14clk: rmobile: Add R8A77990 RPC clockMarek Vasut1-0/+5
2018-06-02Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini5-32/+386
2018-06-01clk: renesas: Add R8A77990 E3 clock tablesMarek Vasut3-0/+311
2018-06-01clk: renesas: Add PE clock handlingMarek Vasut2-6/+40
2018-06-01clk: renesas: Add PLL1 and PLL3 dividersMarek Vasut1-4/+8
2018-06-01clk: renesas: Pass clock rate around as 64bit number internallyMarek Vasut1-25/+31
2018-06-01clk: renesas: Fix swapped arguments in debug messageMarek Vasut1-1/+1
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini9-18/+9
2018-05-02clk: renesas: Drop USB extal from the R8A7792 clock driverMarek Vasut1-2/+0
2018-04-21clk: renesas: Minor clean up of the R8A7794 clock driverMarek Vasut1-7/+3
2018-04-21clk: renesas: Minor clean up of the R8A7792 clock driverMarek Vasut1-7/+3
2018-04-13clk: renesas: Minor clean up of the R8A7790 clock driverMarek Vasut1-7/+3
2018-03-05clk: renesas: Add R8A77965 M3N entriesMarek Vasut1-0/+19
2018-02-16clk: rmobile: Assure SD-IF clock are configured correctlyMarek Vasut1-0/+2
2018-01-27Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini16-1104/+3094
2018-01-24clk: renesas: Import R8A7794 E2 clock tablesMarek Vasut3-0/+284
2018-01-24clk: renesas: Import R8A7792 V2H clock tablesMarek Vasut3-0/+257
2018-01-24clk: renesas: Import R8A7791/R8A7793 M2 clock tablesMarek Vasut3-0/+308
2018-01-24clk: renesas: Import R8A7790 H2 clock tablesMarek Vasut3-0/+303
2018-01-24clk: renesas: Add Gen2 clock coreMarek Vasut5-0/+339
2018-01-24clk: renesas: Add DIV6P1 clock typeMarek Vasut1-0/+6
2018-01-24clk: renesas: Split out code shared between Gen2 and Gen3Marek Vasut4-167/+203
2018-01-24clk: renesas: Make clock tables Kconfig configurableMarek Vasut2-5/+33
2018-01-24clk: renesas: Split SMSTPCR and RMSTPCR tablesMarek Vasut6-30/+57
2018-01-24clk: renesas: Pull Gen3 specific bits into separate headerMarek Vasut6-41/+64
2018-01-24clk: renesas: Make PLL configurations per-SoCMarek Vasut6-51/+178
2018-01-24clk: renesas: Make clk_ids per-driverMarek Vasut6-40/+143
2018-01-24clk: renesas: Split RCar Gen3 driverMarek Vasut7-903/+1052
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas1-2/+2
2017-12-09clk: rmobile: Add R8A77995 D3 clock tablesMarek Vasut1-3/+164
2017-12-09clk: rmobile: Add R8A77970 V3M clock tablesMarek Vasut2-4/+121
2017-12-09clk: rmobile: Fix typo in R8A7796 RPC clock table entryMarek Vasut1-1/+1
2017-11-30clk: rmobile: Add R8A7796 xHCI clockMarek Vasut1-0/+1
2017-11-30clk: rmobile: Move preboot clock shutdown to the driverMarek Vasut1-0/+59
2017-09-24clk: rmobile: Add RPC hyperflash clockMarek Vasut1-1/+43
2017-09-24clk: rmobile: Add support for setting SDxCKCRMarek Vasut1-0/+34
2017-08-26clk: rmobile: Split R8A7795 and R8A7796 core clock tablesMarek Vasut1-33/+96