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author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-04-21 16:36:54 +0200 |
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committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-04-21 18:00:00 +0200 |
commit | 841feae985bd1bd29af119f59cf7f5c74756948c (patch) | |
tree | ed4265959263408374ba261db8649e4077427c71 /drivers/clk/renesas | |
parent | a35747b5e1261adfb27ab87575dea4b17e247da2 (diff) | |
download | u-boot-841feae985bd1bd29af119f59cf7f5c74756948c.tar.gz u-boot-841feae985bd1bd29af119f59cf7f5c74756948c.tar.bz2 u-boot-841feae985bd1bd29af119f59cf7f5c74756948c.zip |
clk: renesas: Minor clean up of the R8A7792 clock driver
The initconst is not used in U-Boot, drop it. The r8a7792_crit_mod_clks
is also not used in U-Boot, so drop it too.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/clk/renesas')
-rw-r--r-- | drivers/clk/renesas/r8a7792-cpg-mssr.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index 260bb892d6..4ba18b18be 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -39,7 +39,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7792_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -78,7 +78,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1), }; -static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7792_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7792_CLK_MP), DEF_MOD("jpu", 106, R8A7792_CLK_M2), DEF_MOD("tmu1", 111, R8A7792_CLK_P), @@ -152,10 +152,6 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), }; -static const unsigned int r8a7792_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -179,7 +175,7 @@ static const unsigned int r8a7792_crit_mod_clks[] __initconst = { #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { { 1, 208, 106, 200 }, { 1, 208, 88, 200 }, { 1, 156, 80, 150 }, |