platform/kernel/u-boot - Domain: System / Kernel;

Age	Commit message (Expand)	Author	Files	Lines
2023-02-17	riscv: Rename Andes cpu and board names	Leo Yu-Chi Liang	5	-0/+0
2023-02-17	configs: ae350: Enable v5l2 cache for AE350 platforms in SPL	Yu Chien Peter Lin	1	-0/+1
2023-02-17	riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL	Yu Chien Peter Lin	1	-30/+68
2023-02-17	riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()	Yu Chien Peter Lin	1	-37/+12
2023-02-17	riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"	Leo Yu-Chi Liang	2	-92/+2
2023-02-01	riscv: ax25: bypass malloc when spl fit boots from ram	Rick Chen	2	-0/+28
2023-02-01	riscv: ae350: Enable CCTL_SUEN	Rick Chen	1	-7/+11
2023-02-01	riscv: cpu: check U-Mode before counteren write	Nikita Shubin	1	-8/+8
2022-11-15	riscv: Fix detecting FPU support in standard extension	Yu Chien Peter Lin	1	-3/+11
2022-11-03	riscv: Rename Andes PLIC to PLICSW	Yu Chien Peter Lin	1	-1/+1
2022-09-26	Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ...	Tom Rini	2	-8/+13
2022-09-26	riscv: Introduce AVAILABLE_HARTS	Rick Chen	2	-5/+10
2022-09-26	spl: introduce SPL_XIP to config	Nikita Shubin	2	-3/+3
2022-09-23	board_f: Fix types for board_get_usable_ram_top()	Pali Rohár	3	-3/+3
2022-08-11	riscv: ae350: Fix XIP config boot failure	Leo Yu-Chi Liang	1	-1/+3
2022-08-11	riscv: cpu: set gp before board_init_f_init_reserve	Nikita Shubin	1	-0/+1
2022-06-23	linker_lists: Rename sections to remove . prefix	Andrew Scull	2	-4/+4
2022-06-06	Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h	Tom Rini	1	-1/+2
2022-03-10	event: Convert arch_cpu_init_dm() to use events	Simon Glass	1	-1/+4
2021-12-02	riscv: Enable SPI flash env for SiFive Unmatched.	Thomas Skibo	1	-0/+13
2021-10-18	riscv: Remove OF_PRIOR_STAGE from RISC-V boards	Ilias Apalodimas	2	-8/+0
2021-10-07	riscv: ae350: enable Coherence Manager for ae350	Leo Yu-Chi Liang	1	-0/+42
2021-10-07	sysreset: provide SBI based sysreset driver	Heinrich Schuchardt	1	-1/+12
2021-09-07	board: sifive: use ccache driver instead of helper function	Zong Li	6	-112/+4
2021-08-17	riscv: cpu: fu740: Fix typo of date	Zong Li	1	-1/+1
2021-07-28	i2c: Rename SPL/TPL_I2C_SUPPORT to I2C	Simon Glass	1	-1/+1
2021-07-06	riscv: sifive: fu740: Support i2c in spl	Zong Li	1	-0/+1
2021-07-06	riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller	Zong Li	1	-0/+2
2021-05-31	riscv: cpu: fu740: clear feature disable CSR	Green Wan	1	-0/+15
2021-05-31	drivers: clk: add fu740 support	Green Wan	1	-1/+1
2021-05-31	riscv: cpu: fu740: Add support for cpu fu740	Green Wan	6	-0/+187
2021-05-24	treewide: Convert macro and uses of __section(foo) to __section("foo")	Marek Behún	1	-2/+2
2021-05-19	riscv: qemu: Switch to use binman to generate u-boot.itb	Bin Meng	1	-0/+1
2021-05-17	riscv: Split SiFive CLINT support between SPL and U-Boot proper	Bin Meng	2	-2/+3
2021-05-14	Revert "riscv: cpu: fu740: clear feature disable CSR"	Bin Meng	1	-15/+0
2021-05-05	riscv: cpu: fu740: clear feature disable CSR	Green Wan	1	-0/+15
2021-05-05	riscv: cpu: Add callback to init each core	Green Wan	2	-0/+15
2021-03-27	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	Simon Glass	3	-3/+3
2021-02-15	Merge branch '2021-02-02-drop-asm_global_data-when-unused'	Tom Rini	3	-0/+3
2021-02-03	riscv: Adjust board_get_usable_ram_top() for 32-bit	Bin Meng	2	-8/+6
2021-02-02	common: Drop asm/global_data.h from common header	Simon Glass	3	-0/+3
2020-12-14	riscv: fix the wrong swap value register	Brad Kim	1	-1/+1
2020-11-28	riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller	Pragnesh Patel	1	-0/+2
2020-10-26	timer: Add _TIMER suffix to Andes PLMT Kconfig	Sean Anderson	1	-1/+1
2020-09-30	riscv: Add some comments to start.S	Sean Anderson	1	-2/+17
2020-09-30	riscv: Ensure gp is NULL or points to valid data	Sean Anderson	1	-3/+25
2020-09-30	riscv: Consolidate fences into AMOs for available_harts_lock	Sean Anderson	1	-6/+3
2020-09-30	riscv: Clear pending IPIs on initialization	Sean Anderson	1	-0/+20
2020-09-30	Revert "riscv: Clear pending interrupts before enabling IPIs"	Sean Anderson	1	-2/+0
2020-09-30	riscv: Rework riscv timer driver to only support S-mode	Sean Anderson	3	-3/+3