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| author | Green Wan <green.wan@sifive.com> | 2021-05-27 06:52:14 -0700 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-05-31 16:35:55 +0800 |
| commit | c552debbd8f2b852de669a7e30e8aa1aef4fa463 (patch) | |
| tree | 2859a73272d410809a08b040f804123ddf4d64b8 /arch/riscv/cpu | |
| parent | 70415e1e528db0856fedd4fa79b9f4a303a28c62 (diff) | |
| download | u-boot-c552debbd8f2b852de669a7e30e8aa1aef4fa463.tar.gz u-boot-c552debbd8f2b852de669a7e30e8aa1aef4fa463.tar.bz2 u-boot-c552debbd8f2b852de669a7e30e8aa1aef4fa463.zip | |
riscv: cpu: fu740: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/cpu')
| -rw-r--r-- | arch/riscv/cpu/fu740/spl.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c index ea0b2283a2..55e30346ff 100644 --- a/arch/riscv/cpu/fu740/spl.c +++ b/arch/riscv/cpu/fu740/spl.c @@ -6,6 +6,9 @@ #include <dm.h> #include <log.h> +#include <asm/csr.h> + +#define CSR_U74_FEATURE_DISABLE 0x7c1 int spl_soc_init(void) { @@ -21,3 +24,15 @@ int spl_soc_init(void) return 0; } + +void harts_early_init(void) +{ + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); +} |