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2023-02-17cpsw_mdio.c: Use correct reg in cpsw_mdio_get_aliveUlf Samuelsson1-3/+3
cpsw_mdio_get_alive reads the wrong register. See page 2316 in SPRUH73Q AM335x TRM Signed-off-by: Ulf Samuelsson <ulf@emagii.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-02-17configs: Resync with savedefconfigTom Rini718-1775/+1572
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-17Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini32-321/+331
- binman: Add help message if opensbi is absent when building u-boot SPL - AndesTech: rename cpu and board name to 'andesv5' and 'ae350' - Clean up cache operation for Andes ae350 platform
2023-02-17riscv: binman: Add help message for missing blobsRick Chen2-0/+7
Add the 'missing-msg' for more detailed output on missing system firmware. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-02-17riscv: ae350: Adjust the memory layout of ae350Leo Yu-Chi Liang4-12/+12
Adjust the initial stack pointer address to 0x10000000(256M) Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang22-30/+30
The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17driver: cache-v5l2: Fix type casting warning on RV32Yu Chien Peter Lin1-1/+1
This patch fixes following warning for the riscv32 toolchain. drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17configs: ae350: Display CPU and board info for AE350 platformsYu Chien Peter Lin8-0/+16
Display information about CPU and board during start up. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17configs: ae350: Increase maximum retry count for AE350 platformsYu Chien Peter Lin8-0/+8
Loading an image via TFTP is often interrupted when retrying more than 10 times, increase the number of retries so that it does not simply stop the transfer. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17configs: ae350: Enable v5l2 cache for AE350 platforms in SPLYu Chien Peter Lin5-0/+9
To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit: ca06444aac2c643db3a3f2eb37afc60fae15177e Turing on does not significantly increase the size of u-boot-spl.bin, so we enable it by default to improve performance. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPLYu Chien Peter Lin1-30/+68
This patch refines L1 cache enable/disable and v5l2-cache enable functions. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin3-3/+3
Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()Yu Chien Peter Lin2-37/+43
As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platformYu Chien Peter Lin1-8/+24
The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()Yu Chien Peter Lin1-8/+9
The L2-cache is not enabled currently, the enbale_caches() will call the v5l2_enable() callback to enable it in SPL. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang3-93/+2
There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: global_data.h: Correct the comment for PLICSWYu Chien Peter Lin1-1/+1
PLIC is used for external interrupt, while PLICSW is an Andes-specific design for software interrupt. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-13Prepare v2023.04-rc2Tom Rini2-2/+4
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-13clocks: qcs404: Add support for I2C clocksSumit Garg2-0/+75
Co-developed-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-13Merge tag 'i2c-updates-for-v2023.04' of ↵Tom Rini9-13/+527
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c updates for v2023.04 - add new i2c driver ast2600 from Ryan Chen - i2c-cdns: make read fifo-depth configurable through device tree from Pei Yue Ho - mxc i2c driver: print base address in hex, not in decimal from Fabio
2023-02-13Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini18-7/+1358
- mvebu: Support for 2 new Armada 385 boards (Tony) - mvebu: Minor misc board enhancements (Tony) - kirkwood: Serial driver fixes (Kconfig & dtsi) (Tony) - cmd: return code when tlv_eeprom incorrectly called (Heinrich)
2023-02-13arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 boardTony Dinh1-0/+7
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is required for this board to boot over UART with kwboot. Enable this in kirkwood-pogoplug-series-4-u-boot.dtsi. Added by Stefan while applying: Please note that it's not fully understood, why this property really is needed. Here a link to the discussion about this: https://lore.kernel.org/r/20230201080210.ypz4nrj4y2igwxz3@pali/ Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13arm: mvebu: Add support for Synology DS116 (Armada 385)Tony Dinh8-0/+595
Synology DS116 is a NAS based on Marvell Armada 385 SoC. Board Specification: - Marvel MV88F6820 Dual Core at 1.8GHz - 1 GiB DDR3 RAM - 8MB Macronix mx25l6405d SPI flash - I2C - 2x USB 3.0 - 1x GBE LAN port (PHY: Marvell 88E1510) - 1x SATA (6 Gbps) - 3x LED - PIC16F1829 (connected to uart1) - GPIO fan - serial console Note that this patch depends on the add-support for Thecus N2350 patch: https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-02-13arm: mvebu: Power up 2nd SATA port for Thecus N2350Tony Dinh1-2/+2
Currently, only the 1st SATA port is powered up (by GPIO1 12). Add GPIO1 13 in board initialization to power up the 2nd SATA port. Note that this patch depends on the initial add-support patch: https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13arm: kirkwood: sheevaplug: reduce u-boot image sizeTony Dinh1-0/+5
Sheevaplug board has 512K CONFIG_BOARD_SIZE_LIMIT. Recently, DM_SERIAL has pushed the image size a few hundred bytes over that limit. So explicitly deselect some configs that are unrelated to this board (and gain back a bit over 2K). Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-02-13arm: mvebu: Add support for Thecus N2350 (Armada 385) boardTony Dinh8-0/+746
Thecus N2350 is a NAS based on Marvell Armada 385 SoC. Specification: - Processor: Marvel MV88F6820 Dual Core at 1GHz - 1 GiB DDR4 RAM - 4MB Macronix mx25l3205d SPI flash - 512MB Hynix H27U4G8F2DTR-BC NAND flash - I2C - 2x USB 3.0 - 1x GBE LAN port (PHY: Marvell 88E1510) - 2x SATA (hot swap slots) - 3x buttons - 10x LEDS - serial console Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13arm: kirkwood: Use CONFIG_SYS_NS16550 with DM_SERIAL for Kirkwood boardsTony Dinh1-0/+1
CONFIG_SYS_NS16550 is required when DM_SERIAL is enabled for Kirkwood boards. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13cmd: return code when tlv_eeprom incorrectly calledHeinrich Schuchardt1-7/+4
A command called with incorrect parameters should set $? to 1 (false). Instead of calling cmd_usage(cmdtp) and then returning 0 just return CMD_RET_FAILURE. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13i2c: i2c-cdns.c: Update driver to read fifo-depth from device treePei Yue Ho1-12/+18
Enable driver to fetch the optional parameter (fifo-depth) from device tree. If the parameter is not found in the device tree, it will use the default value declared in the driver. Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13dt-bindings: i2c: i2c-cdns.txt: Add description for an optional parameter, ↵Pei Yue Ho1-0/+4
fifo-depth Add description for fifo-depth parameter that can be used in the device tree. Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13arm: aspeed: dtsi: add reg for i2cRyan Chen1-0/+1
The i2c driver have global register that i2c bus use ofnode_get_parent to get parent register address. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c:aspeed:support ast2600 i2c new register mode driverRyan Chen5-0/+503
Add i2c new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c: mxc_i2c: Use hex notation for the base addressFabio Estevam1-1/+1
Printing the I2C controller base address in decimal notation is not helpful. Change it to hex notation, which is the standard format found in the Reference Manual and devicetree. Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-12Merge tag 'dm-pull-12feb23' of ↵Tom Rini3-53/+51
https://source.denx.de/u-boot/custodians/u-boot-dm minor changes to fdt command and binman
2023-02-12cmd: fdt: allow standalone "fdt move"Andre Przywara1-11/+17
At the moment every subcommand of "fdt", except "addr" itself, requires the DT address to be set first. We explicitly check for that before even comparing against the subcommands' string. This early bailout also affects the "move" subcommand, even though that does not require or rely on a previous call to "fdt addr". In fact it even sets the FDT address to the target of the move command, so is a perfect beginning for a sequence of fdt commands. Move the check for a previously set FDT address to after we handle the "move" command also, so we don't need a dummy call to "fdt addr" first, before being able to move the devicetree. This skips one pointless "fdt addr" call in scripts which aim to alter the control DT, but need to copy it to a safe location first (for instance to $fdt_addr_r). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-12cmd: fdt: move: Use map_sysmem to convert pointersAndre Przywara1-3/+3
The "fdt move" subcommand was using the provided DTB addresses directly, without trying to "map" them into U-Boot's address space. This happened to work since on the vast majority of "real" platforms there is a simple 1:1 mapping of VA to PAs, so either value works fine. However this is not true on the sandbox, so the "fdt move" command fails there miserably: => fdt addr $fdtcontroladdr => cp.l $fdtcontroladdr $fdt_addr_r 40 # simple memcpy works => fdt move $fdtcontroladdr $fdt_addr_r Segmentation fault Use the proper "map_sysmem" call to convert PAs to VAs, to make this more robust in general and to enable operation in the sandbox. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-12binman: Show the image name for the top-level sectionSimon Glass2-39/+31
At present we show 'main section' as the top-level section name. It may be more helpful to show the actual image name. This is tricky because Image is a parent class of Entry_section, so there is no distinction between an image and a section. Update it to show the image name. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-12socfpga: fix the serial console on DE1-SoCJade Lovelace1-0/+1
Previously, the TX LED would flash but nothing would appear on the serial port, and the board would appear dead with a build of the socfpga_cyclone5_defconfig. I have verified that adding the frequency to the uart will fix the serial console on my board. Thanks to @ehoffman on the Rocketboards forum: https://forum.rocketboards.org/t/cyclonev-programming-fpga-from-u-boot/2230/30 Signed-off-by: Jade Lovelace <lists@jade.fyi> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-12Merge tag 'clk-2023.04-rc1' of ↵Tom Rini9-37/+41
https://source.denx.de/u-boot/custodians/u-boot-clk Clock changes for 2023.04-rc1 This contains various fixes and small features. I've included a reset patch as well since it was in the same series as a clock patch.
2023-02-12Merge branch 'for-2023.04' of ↵Tom Rini29-140/+2129
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx - A fix for a long standing bug that has been exposed by commit 50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards from booting since u-boot 2023.01 - A GPIO driver for powerpc 8xx chip - Fixup for powerpc 8xx SPI driver - A new powerpc 8xx board - The two devices having that board.
2023-02-12reset: Allow reset_get_by_name() with NULL nameSamuel Holland3-8/+10
This allows devm_reset_control_get(dev, NULL) to work and get the first reset control, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
2023-02-12clk: Allow clk_get_by_name() with NULL nameSamuel Holland3-7/+14
This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-02-12cmd: clk: probe the clock before dump themPatrick Delaunay1-10/+5
The clock UCLASS need to be probed to allow availability of the private data (struct clk *), get in show_clks() with dev_get_clk_ptr() before use them. Without this patch the clock dump can cause crash because all the private data are not available before calling the API clk_get_rate(). It is the case for the SCMI clocks, priv->channel is needed for scmi_clk_get_rate() and it is initialized only in scmi_clk_probe(). This issue causes a crash for "clk dump" command on STM32MP135F-DK board for SCMI clock not yet probed. Fixes: 1a725e229096 ("clk: fix clock tree dump to properly dump out every registered clock") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221213145708.v2.1.Ia0bc6b272f1e2e3f37873c61d79138c2663c4055@changeid
2023-02-12clk: imx8mn: fix imx8mn_enet_phy_sels clocks listDario Binacchi1-1/+1
[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b] According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV20 010 - SYSTEM_PLL2_DIV8 011 - SYSTEM_PLL2_DIV5 100 - SYSTEM_PLL2_DIV2 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - AUDIO_PLL2_CLK ... ... ... while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for source select bits 101b. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx: rename video_pll1 to video_pllDario Binacchi1-10/+10
[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6] Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx8mn: rename vpu_pll to m7_alt_pllDario Binacchi1-1/+1
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df] The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurrence of its pll. From an analysis of the code and the RM itself, I think vpu pll is used instead of m7 alternate pll, probably for copy and paste of code taken from modules of similar architectures. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
2023-02-12clk: nuvoton: fix bug for calculate pll clockJim Liu1-1/+1
Fix bug for npcm7xx bmc calculate pll clock. PLLCON1 need to divide by 2. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
2023-02-12lmb: Treat a region which is a subset as equalSjoerd Simons1-1/+3
In various cases logical memory blocks are coalesced; As a result doing a strict check whether memory blocks are the same doesn't necessarily work as a previous addition of a given block might have been merged into a bigger block. Fix this by considering a block is already registered if it's a pure subset of one of the existing blocks. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
2023-02-12Merge branch '2023-02-10-update-trace-feature-to-work-with-trace-cmd'Tom Rini26-229/+2347
To quote the author: Since U-Boot's tracing feature was originally written, quite a few changes have taken place in this domain. The original text format used by tracing is still emitted by Linux, but a new trace-cmd tool has invented a binary format which is now used by new tools, such as kernelshark. With recent distributions and the move to Python 3, the old pybootchart tool does not build or run. Unfortunately there is no 1:1 replacement for the features that were provided by pybootchart, or at least it is not obvious. Still, it makes sense to keep with the times. This series updates proftool to use the new binary format, adding support for function and funcgraph tracing, so that U-Boot's trace records can be examined by trace-cmd and kernelshark. This series also adds support for a flamegraph, which provides a visual way to see which functions are called a lot, as well as which ones consume the most time. Some minor updates to the trace implementation within U-Boot are included, to provide a little more information and to fix a few problems. No unit tests are provided by proftool, but a functional test ensures that sandbox can emit traces which can be processed by proftool, then parsed by trace-cmd and that the timing of the various formats looks consistent.
2023-02-11CI, Docker: Update to Jammy 2023016 tagTom Rini3-3/+3
Move to the latest tag for "Jammy" and rebuild the containers. Signed-off-by: Tom Rini <trini@konsulko.com>
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