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| author | Jim Liu <jim.t90615@gmail.com> | 2022-11-21 17:15:28 +0800 |
|---|---|---|
| committer | Sean Anderson <seanga2@gmail.com> | 2023-02-12 12:39:46 -0500 |
| commit | 07f5399f04781568cd8df1cc97c9325d47566289 (patch) | |
| tree | 004952f43cbc9eb695e2013b7755b242d4c4f32e | |
| parent | 78d1c3949a6f85f64b31ee8ab8240392a67ca30e (diff) | |
| download | u-boot-07f5399f04781568cd8df1cc97c9325d47566289.tar.gz u-boot-07f5399f04781568cd8df1cc97c9325d47566289.tar.bz2 u-boot-07f5399f04781568cd8df1cc97c9325d47566289.zip | |
clk: nuvoton: fix bug for calculate pll clock
Fix bug for npcm7xx bmc calculate pll clock.
PLLCON1 need to divide by 2.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
| -rw-r--r-- | drivers/clk/nuvoton/clk_npcm7xx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/nuvoton/clk_npcm7xx.c b/drivers/clk/nuvoton/clk_npcm7xx.c index a12aaa2f4c..b23dd37af6 100644 --- a/drivers/clk/nuvoton/clk_npcm7xx.c +++ b/drivers/clk/nuvoton/clk_npcm7xx.c @@ -25,7 +25,7 @@ static const struct parent_data apb_parent[] = {{NPCM7XX_CLK_AHB, 0}}; static struct npcm_clk_pll npcm7xx_clk_plls[] = { {NPCM7XX_CLK_PLL0, NPCM7XX_CLK_REFCLK, PLLCON0, 0}, - {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, 0}, + {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, POST_DIV2}, {NPCM7XX_CLK_PLL2, NPCM7XX_CLK_REFCLK, PLLCON2, 0}, {NPCM7XX_CLK_PLL2DIV2, NPCM7XX_CLK_REFCLK, PLLCON2, POST_DIV2} }; |