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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-07-10 23:43:13 -0700 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-08-15 13:42:28 +0800 |
| commit | 4d2583dba13f9313f21fb58fb3a4c51b11770e44 (patch) | |
| tree | 26cf69a122a61b2a54ff75b6489414353cff1348 /arch/riscv/cpu | |
| parent | 268753f8e6e7e201966763c53acfea84941ed544 (diff) | |
| download | u-boot-4d2583dba13f9313f21fb58fb3a4c51b11770e44.tar.gz u-boot-4d2583dba13f9313f21fb58fb3a4c51b11770e44.tar.bz2 u-boot-4d2583dba13f9313f21fb58fb3a4c51b11770e44.zip | |
riscv: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers
because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR
numbers as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not
recognize newly added CSRs by name.
This commit is inspired from Linux kernel commit a3182c91ef4e
("RISC-V: Access CSRs using CSR numbers").
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/cpu')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 9 | ||||
| -rw-r--r-- | arch/riscv/cpu/start.S | 3 |
2 files changed, 5 insertions, 7 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index e9a8b437ed..5ca185745e 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -7,7 +7,6 @@ #include <cpu.h> #include <dm.h> #include <log.h> -#include <asm/csr.h> #include <asm/encoding.h> #include <dm/uclass-internal.h> @@ -48,7 +47,7 @@ static inline bool supports_extension(char ext) return false; #else /* !CONFIG_CPU */ #ifdef CONFIG_RISCV_MMODE - return csr_read(misa) & (1 << (ext - 'a')); + return csr_read(CSR_MISA) & (1 << (ext - 'a')); #else /* !CONFIG_RISCV_MMODE */ #warning "There is no way to determine the available extensions in S-mode." #warning "Please convert your board to use the RISC-V CPU driver." @@ -82,7 +81,7 @@ int arch_cpu_init_dm(void) /* Enable FPU */ if (supports_extension('d') || supports_extension('f')) { csr_set(MODE_PREFIX(status), MSTATUS_FS); - csr_write(fcsr, 0); + csr_write(CSR_FCSR, 0); } if (CONFIG_IS_ENABLED(RISCV_MMODE)) { @@ -90,11 +89,11 @@ int arch_cpu_init_dm(void) * Enable perf counters for cycle, time, * and instret counters only */ - csr_write(mcounteren, GENMASK(2, 0)); + csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); /* Disable paging */ if (supports_extension('s')) - csr_write(satp, 0); + csr_write(CSR_SATP, 0); } return 0; diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 60ac8c621e..e06db404f5 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -13,7 +13,6 @@ #include <config.h> #include <common.h> #include <elf.h> -#include <asm/csr.h> #include <asm/encoding.h> #include <generated/asm-offsets.h> @@ -41,7 +40,7 @@ secondary_harts_relocation_error: .globl _start _start: #ifdef CONFIG_RISCV_MMODE - csrr a0, mhartid + csrr a0, CSR_MHARTID #endif /* save hart id and dtb pointer */ |