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author | Jonghwa Lee <jonghwa3.lee@samsung.com> | 2013-11-04 16:12:26 +0900 |
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committer | Chanho Park <chanho61.park@samsung.com> | 2014-03-20 17:42:04 +0900 |
commit | b4065d4d172fefc68e6c132de79bca9a537cb6ba (patch) | |
tree | 15994b40c7f8f52263cc5a076e9469b06eee41eb /drivers/thermal | |
parent | 37aa56caf94ca8fd82a12954e0cf1bbf761436dc (diff) | |
download | linux-3.10-b4065d4d172fefc68e6c132de79bca9a537cb6ba.tar.gz linux-3.10-b4065d4d172fefc68e6c132de79bca9a537cb6ba.tar.bz2 linux-3.10-b4065d4d172fefc68e6c132de79bca9a537cb6ba.zip |
Revert "thermal: exynos: Set MUX bits in tmu's control register to work correctly."
This reverts commit e612d47f36eb9eb90ee88fd11addfe5aac8cdae4.
This will be suppported later with Lukasz's pathches.
Signed-off-by : Jonghwa Lee <jonghwa3.lee@samsung.com>
Diffstat (limited to 'drivers/thermal')
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu.c | 10 | ||||
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu_data.h | 3 |
2 files changed, 0 insertions, 13 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index fa6631a999b..b43afda8acd 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -322,16 +322,6 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on) con |= pdata->reference_voltage << reg->buf_vref_sel_shift; } - /* - * In Exynos 4x12 and 5250, - * MUX bits should be set to 0x6 for normal operation. - * For ohters, it can be ignored. - */ - if (pdata->type == SOC_ARCH_EXYNOS) { - con &= ~(EXYNOS_TMU_MUX_ADDR_MASK << EXYNOS_TMU_MUX_ADDR_SHIFT); - con |= EXYNOS_TMU_MUX_ADDR_DEFAULT << EXYNOS_TMU_MUX_ADDR_SHIFT; - } - if (pdata->gain) { con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift); con |= (pdata->gain << reg->buf_slope_sel_shift); diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h index 2144eaf5419..dc7feb51099 100644 --- a/drivers/thermal/samsung/exynos_tmu_data.h +++ b/drivers/thermal/samsung/exynos_tmu_data.h @@ -35,9 +35,6 @@ #define EXYNOS_TMU_TEMP_MASK 0xff #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f -#define EXYNOS_TMU_MUX_ADDR_DEFAULT 0x6 -#define EXYNOS_TMU_MUX_ADDR_MASK 0x7 -#define EXYNOS_TMU_MUX_ADDR_SHIFT 20 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 #define EXYNOS_TMU_CORE_EN_SHIFT 0 |