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authorJonghwa Lee <jonghwa3.lee@samsung.com>2013-11-04 14:23:22 +0900
committerChanho Park <chanho61.park@samsung.com>2014-03-20 17:42:03 +0900
commit37aa56caf94ca8fd82a12954e0cf1bbf761436dc (patch)
treeefb63e2deb074a0765736d9b5905fdaa4f4e507b /drivers/thermal
parentde0f00fdd686d1712924a44a554b86e0e2fbfa08 (diff)
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thermal: exynos: Set MUX bits in tmu's control register to work correctly.
Exynos 4x12 and 5250 need that MUX bits in control register is set to be certain value at reset. Otherwise it'll reflect improper data when we read current sensor's value. For other Exynos series, it doesn't need. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Diffstat (limited to 'drivers/thermal')
-rw-r--r--drivers/thermal/samsung/exynos_tmu.c10
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.h3
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index b43afda8acd..fa6631a999b 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -322,6 +322,16 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
}
+ /*
+ * In Exynos 4x12 and 5250,
+ * MUX bits should be set to 0x6 for normal operation.
+ * For ohters, it can be ignored.
+ */
+ if (pdata->type == SOC_ARCH_EXYNOS) {
+ con &= ~(EXYNOS_TMU_MUX_ADDR_MASK << EXYNOS_TMU_MUX_ADDR_SHIFT);
+ con |= EXYNOS_TMU_MUX_ADDR_DEFAULT << EXYNOS_TMU_MUX_ADDR_SHIFT;
+ }
+
if (pdata->gain) {
con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
con |= (pdata->gain << reg->buf_slope_sel_shift);
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index dc7feb51099..2144eaf5419 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -35,6 +35,9 @@
#define EXYNOS_TMU_TEMP_MASK 0xff
#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
+#define EXYNOS_TMU_MUX_ADDR_DEFAULT 0x6
+#define EXYNOS_TMU_MUX_ADDR_MASK 0x7
+#define EXYNOS_TMU_MUX_ADDR_SHIFT 20
#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
#define EXYNOS_TMU_CORE_EN_SHIFT 0