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2010-03-27tcg-mips: add guest base supportAurelien Jarno2-29/+39
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27tcg/mips: implement the not_i32 op the same way as gccAurelien Jarno1-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27tcg-mips: implement norAurelien Jarno2-1/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson11-24/+37
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson10-0/+29
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson10-0/+29
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson11-1/+30
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Use not_i32 to implement not_i64.Richard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Change TCGType to an enumeration.Richard Henderson2-9/+12
The TCGType name was already used consistently. Changing it to an enumeration instead of a set of defines aids debugging. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson7-37/+39
Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Name the opcode enumeration.Richard Henderson12-63/+78
Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini9-24/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23tcg-hppa: Fix 64-bit argument orderingRichard Henderson1-1/+11
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg/arm: don't save/restore r7 in prologue/epilogueAurelien Jarno1-6/+6
There is no need to save r7, it is used to store the address of the env structure and is not modified by GCC. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg/arm: fix load/store definitions for 32-bit targetsAurelien Jarno1-0/+14
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg: protect div2 in tcg/tcg-opc.hAurelien Jarno1-2/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg: declare internal helpers as const and pureAurelien Jarno1-4/+9
TCG internal helpers only access to the values passed in arguments, and do not modify the CPU internal state. Thus they can be declared as const and pure. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg/arm: use helpers for divu/remuAurelien Jarno2-95/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg: add div/rem 32-bit helpersAurelien Jarno6-2/+65
Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13Fix build with -DNDEBUG in CFLAGSBlue Swirl1-1/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13tcg/arm: implement andc opAurelien Jarno2-1/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg: update README with const and pure helpersAurelien Jarno1-4/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno1-4/+7
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes on ARM hosts. This is not a bug of this commit, but a latent bug revealed by this commit. The TCG code is called through a procedure call using the prologue and epilogue code. This code does not save and restore enough registers. The "Procedure Call Standard for the ARM Architecture" says: A subroutine must preserve the contents of the registers r4-r8, r10,  r11 and SP (and r9 in PCS variants that designate r9 as v6). The current code only saves and restores r9 to r11, and misses r4 to r8. The patch fixes that by saving r4 to r12. Theoretically there is no need to save and restore r12, but an even number of registers have to be saved as per EABI. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13Fix Sparc host build breakageBlue Swirl1-0/+8
Fix error: CC sparc-bsd-user/op_helper.o In file included from /src/qemu/tcg/tcg.c:158: /src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc2-0/+5
Signed-off-by: malc <av1474@comtv.ru>
2010-03-12Remove TLB from userspacePaul Brook3-0/+6
Remove TLB from userspace CPU structure. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno1-14/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno1-6/+20
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02Add a missing breakAndrzej Zaborowski1-0/+1
2010-03-02tcg/arm: implement setcond2Aurelien Jarno1-0/+11
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: implement setcondAurelien Jarno1-0/+9
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: fix div2/divu2Aurelien Jarno1-6/+24
When restoring register values, increase the stack register for skipped values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-02-27tcg/ppc: Fix right rotationmalc1-1/+2
Signed-off-by: malc <av1474@comtv.ru>
2010-02-23tcg/ppc: Fix typomalc1-1/+1
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg/ppc64: Use C90 style commentsmalc1-18/+18
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg/ppc: Implement some of the optional opsmalc2-8/+88
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad3-3/+4
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
2010-02-20tcg: fix assertion with --enable-debugJay Foad1-5/+0
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the following assertion failure: qemu-alpha: tcg/tcg.c:1055: tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson8-17/+106
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ORC.Richard Henderson2-0/+7
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ANDC.Richard Henderson2-0/+8
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ORC.Richard Henderson2-0/+17
Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ANDC.Richard Henderson2-0/+17
Previously ANDC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement not.Richard Henderson2-0/+8
The fallback implementation of "ret = arg1 ^ -1" isn't ideal because of the extra tcg op to load the minus one. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement neg.Richard Henderson2-2/+16
The fallback implementation of "ret = 0 - arg1" isn't ideal, first because of the extra tcg op to load the zero, and second because we fail to handle zero as %g0 for arg1 of the sub. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc1-12/+12
Signed-off-by: malc <av1474@comtv.ru>
2010-02-20Use ppc host calling convention definitions to set ↵Juergen Lock1-3/+3
TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}. New version after malc's comments. (This avoids having to do #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__ for the third case.) Submitted by: Andreas Tobler <andreast@fgznet.ch> (original version) Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: malc <av1474@comtv.ru>
2010-02-18tcg: Add consistency checks for op definitionsStefan Weil2-0/+24
When compiled with CONFIG_DEBUG_TCG, this code looks for missing, duplicate and wrong entries in the op definitions. Errors will raise an assertion at program start (all checks are done in the initial phase). The current code contains such errors, at least for i386 guest on i386 host. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg-sparc: Implement setcond, setcond2.Richard Henderson1-0/+127
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg: Add tcg_swap_cond.Richard Henderson1-0/+8
Returns the condition as if with swapped comparison operands. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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