summaryrefslogtreecommitdiff
path: root/tcg/ppc/tcg-target.c
AgeCommit message (Expand)AuthorFilesLines
2012-09-22tcg/ppc32: Implement movcond32malc1-0/+75
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil1-6/+0
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl1-38/+0
2012-06-24TCG: Fix compile breakage in tcg_dump_opsAlexander Graf1-1/+1
2012-05-27tcg/ppc: Handle _CALL_DARWIN being undefined on DarwinAndreas Färber1-6/+10
2012-05-09tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 modeAndreas Färber1-1/+32
2012-05-09tcg/ppc: Clobber r5 for 64-bit qemu_ldAndreas Färber1-0/+3
2012-05-09tcg/ppc: Don't hardcode register numbersAndreas Färber1-12/+17
2012-05-09tcg/ppc: Do not overwrite lower address word on Darwin and AIXAndreas Färber1-4/+0
2012-05-03Bail out if CONFIG_TCG_PASS_AREG0 is definedmalc1-21/+1
2012-03-18softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl1-0/+45
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-2/+2
2011-11-14tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson1-4/+4
2011-09-01tcg/ppc/tcg-target.c: Avoid 'set but not used' gcc warningsPeter Maydell1-10/+10
2011-08-22tcg/ppc32: implement deposit_i32malc1-0/+12
2011-06-28TCG/PPC: use stack for TCG tempsBlue Swirl1-2/+5
2011-06-28tcg/ppc: Remove tcg_out_addimalc1-5/+0
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl1-0/+2
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl1-3/+3
2010-06-29tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson1-4/+4
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson1-2/+2
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson1-24/+24
2010-04-18tcg/ppc: Remove redundant comparison from brcond2malc1-2/+1
2010-04-17tcg/ppc: Fix signed versions of brcond2malc1-1/+2
2010-04-06tcg/ppc: Fix typomalc1-1/+1
2010-04-06tcg/ppc: Implment bswap16/32malc1-0/+75
2010-04-05tcg/ppc: Implement eqv, nand and normalc1-0/+14
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook1-10/+2
2010-04-04tcg/ppc: Fix not_i32malc1-1/+1
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-3/+3
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson1-3/+4
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc1-0/+3
2010-02-27tcg/ppc: Fix right rotationmalc1-1/+2
2010-02-23tcg/ppc: Fix typomalc1-1/+1
2010-02-22tcg/ppc: Implement some of the optional opsmalc1-0/+80
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad1-2/+0
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc1-12/+12
2010-02-07tcg/ppc32: proper setcond implementationmalc1-25/+25
2010-02-07tcg/ppc32: implement setcond[2]malc1-14/+157
2009-09-27tcg/ppc: always use tcg_out_callmalc1-20/+10
2009-09-06When targeting PPU use rlwinm instead of andi. if possiblemalc1-8/+54
2009-07-20Fix rbase initializationmalc1-1/+1
2009-07-18PPC 32/64 GUEST_BASE supportmalc1-21/+63
2009-07-18Fix LHZX opcode valuemalc1-1/+1
2009-04-11Whack [LS]MWmalc1-3/+0
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc1-3/+0
2009-02-11Add missing r24..r26 to calle save registersmalc1-0/+5
2009-01-26R13 is reserved for small data area pointer by SVR4 PPC ABImalc1-0/+5
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 19:07:42 +0000