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path: root/target-xtensa/translate.c
AgeCommit message (Expand)AuthorFilesLines
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov1-104/+126
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov1-0/+1
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov1-0/+13
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-2/+2
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-10target-xtensa: avoid using cpu_single_envBlue Swirl1-5/+5
2012-10-06target-xtensa: de-optimize EXTUIAurelien Jarno1-20/+2
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov1-0/+38
2012-09-22target-xtensa: implement FP1 groupMax Filippov1-1/+80
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov1-0/+48
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov1-1/+60
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov1-4/+54
2012-09-22target-xtensa: add FP registersMax Filippov1-7/+45
2012-09-21target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov1-1/+3
2012-09-21target-xtensa: fix extui shift amountMax Filippov1-3/+21
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov1-2/+14
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov1-30/+34
2012-06-09target-xtensa: fix CCOUNT for conditional branchesMax Filippov1-0/+2
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov1-1/+1
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov1-0/+2
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova1-3/+3
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber1-11/+11
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov1-0/+30
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov1-1/+48
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov1-3/+65
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov1-0/+6
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov1-1/+2
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov1-1/+6
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov1-1/+1
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov1-7/+7
2011-10-15target-xtensa: implement MAC16 optionMax Filippov1-1/+134
2011-09-10target-xtensa: implement boolean optionMax Filippov1-24/+85
2011-09-10target-xtensa: implement memory protection optionsMax Filippov1-5/+86
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov1-0/+1
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov1-0/+7
2011-09-10target-xtensa: implement accurate window checkMax Filippov1-0/+110
2011-09-10target-xtensa: implement interrupt optionMax Filippov1-10/+143
2011-09-10target-xtensa: implement SIMCALLMax Filippov1-1/+8
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov1-3/+44
2011-09-10target-xtensa: implement extended L32RMax Filippov1-4/+33
2011-09-10target-xtensa: implement loop optionMax Filippov1-9/+68
2011-09-10target-xtensa: implement windowed registersMax Filippov1-9/+136
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov1-1/+76
2011-09-10target-xtensa: implement exceptionsMax Filippov1-5/+102
2011-09-10target-xtensa: add PS register and access controlMax Filippov1-5/+24
2011-09-10target-xtensa: implement CACHE groupMax Filippov1-1/+94
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