summaryrefslogtreecommitdiff
path: root/target-xtensa/translate.c
AgeCommit message (Expand)AuthorFilesLines
2015-10-21target-xtensa: implement S32NBMax Filippov1-0/+11
2015-10-21target-xtensa: implement depbits instructionMax Filippov1-0/+20
2015-10-21target-xtensa: add window overflow check to L32E/S32EMax Filippov1-2/+4
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-35/+4
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-2/+3
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-0/+3
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-18/+7
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+2
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-4/+1
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-1/+1
2015-07-06target-xtensa: add 64-bit floating point registersMax Filippov1-3/+4
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae1-1/+2
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-9/+9
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-4/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+0
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-12-17target-xtensa: don't generate dead codeMax Filippov1-279/+321
2014-12-17target-xtensa: record available window in TB flagsMax Filippov1-43/+18
2014-12-17target-xtensa: fix translation for opcodes crossing page boundaryMax Filippov1-4/+23
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-3/+2
2014-05-26target-xtensa: fix cross-page jumps/calls at the end of TBMax Filippov1-2/+2
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+3
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov1-2/+7
2014-02-24target-xtensa: add basic checks to icache opcodesMax Filippov1-0/+27
2014-02-24target-xtensa: add basic checks to dcache opcodesMax Filippov1-0/+38
2014-02-24target-xtensa: add RRRI4 opcode format fieldsMax Filippov1-0/+9
2013-10-15target-xtensa: add in_asm loggingMax Filippov1-0/+8
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-2/+0
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-07-29target-xtensa: check register window inlineMax Filippov1-8/+25
2013-07-29target-xtensa: don't generate dead code to access invalid SRsMax Filippov1-13/+18
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov1-2/+1
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
2013-07-09target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber1-4/+5
2013-07-09target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber1-2/+3
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-2/+4
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-02-23target-xtensa: Use add2/sub2 for macRichard Henderson1-16/+13
2013-02-23target-xtensa: Use mul*2 for mul*hiRichard Henderson1-14/+6
2012-12-22target-xtensa: fix search_pc for the last TB opcodeMax Filippov1-1/+5
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-08target-xtensa: use movcond where possibleMax Filippov1-50/+42
2012-12-08target-xtensa: implement MISC SRMax Filippov1-0/+4
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 22:06:35 +0000