index
:
sdk/emulator/qemu
1.0_post
2.0alpha
features/brillcodec_2i
features/camera
features/cnp
features/dr
features/qt_dr
features/smp
features/virtio-9p
features/vmodem
glesv3
master
opensrc_p2.3
opensrc_p2.3.1
opensrc_p2.3.2
opensrc_p2.4
opensrc_p3.0
opensrc_p4.0
sandbox/byungchul.so/tizen
sandbox/elebideau/tizen
sandbox/mmajewski2/maru-virgl-rendering-wip
sandbox/mmajewski2/standalone-virgl-wip
sandbox/pcoval/tizen
spin
tizen
tizen_2.0
tizen_2.1
tizen_2.2
tizen_3.0.m14.4_ivi
tizen_p2.3
tizen_p2.3.1
tizen_qemu_1.6
tizen_qemu_1.7
tizen_qemu_2.0
tizen_qemu_5.0.1
tizen_studio_1.2_p2.3
tizen_studio_1.2_p2.3.1
tizen_studio_1.2_p2.3.2
tizen_studio_1.2_p2.4
tizen_studio_1.2_p3.0
tizen_studio_1.3_p2.3
tizen_studio_1.3_p2.3.1
tizen_studio_1.3_p2.3.2
tizen_studio_1.3_p2.4
tizen_studio_1.3_p3.0
tizen_studio_2.0_p2.3
tizen_studio_2.0_p2.3.1
tizen_studio_2.0_p2.3.2
tizen_studio_2.0_p2.4
tizen_studio_2.0_p3.0
tizen_studio_2.0_p4.0
tizen_studio_2.0_p5.0
tizen_studio_3.0_p2.3
tizen_studio_3.0_p2.3.1
tizen_studio_3.0_p2.3.2
tizen_studio_3.0_p2.4
tizen_studio_3.0_p3.0
tizen_studio_3.0_p4.0
tizen_studio_3.0_p5.0
tizen_studio_3.5_p2.3
tizen_studio_3.5_p2.3.1
tizen_studio_3.5_p2.3.2
tizen_studio_3.5_p2.4
tizen_studio_3.5_p3.0
tizen_studio_3.5_p4.0
tizen_studio_3.5_p5.0
tizen_studio_3.5_p5.5
tizen_studio_4.0_p2.3
tizen_studio_4.0_p2.3.1
tizen_studio_4.0_p2.3.2
tizen_studio_4.0_p2.4
tizen_studio_4.0_p3.0
tizen_studio_4.0_p4.0
tizen_studio_4.0_p5.0
tizen_studio_4.0_p5.5
tizen_studio_4.0_p6.0
tizen_studio_4.5_p6.5
tizen_studio_5.0_p7.0
tizen_studio_5.5_p7.5
tizen_studio_5.5_p8.0
tizen_studio_6.0_p9.0
tizen_studio_p2.3
tizen_studio_p2.3.1
tizen_studio_p2.3.2
tizen_studio_p2.4
tizen_studio_p3.0
tizen_studio_p4.0
works/arg_renewal
Domain: SDK / Emulator;
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-tricore
/
tricore-opcodes.h
Age
Commit message (
Expand
)
Author
Files
Lines
2015-05-22
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+2
2015-05-22
target-tricore: add FRET instructions of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+2
2015-05-22
target-tricore: add FCALL instructions of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+3
2015-05-22
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
Bastian Koppelmann
1
-0
/
+1
2015-05-22
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
Bastian Koppelmann
1
-0
/
+1
2015-05-22
target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
Bastian Koppelmann
1
-0
/
+5
2015-05-22
target-tricore: add CMPSWP instructions of the v1.6.1 ISA
Bastian Koppelmann
1
-0
/
+5
2015-05-11
target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
Bastian Koppelmann
1
-1
/
+1
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...
Bastian Koppelmann
1
-2
/
+2
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...
Bastian Koppelmann
1
-2
/
+2
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...
Bastian Koppelmann
1
-24
/
+24
2015-03-03
target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...
Bastian Koppelmann
1
-4
/
+4
2015-03-03
target-tricore: Add instructions of RRR2 opcode format
Bastian Koppelmann
1
-1
/
+1
2015-01-27
target-tricore: Add instructions of RRR opcode format
Bastian Koppelmann
1
-1
/
+1
2015-01-15
target-tricore: Fix new typos
Stefan Weil
1
-2
/
+2
2014-12-21
target-tricore: Fix MFCR/MTCR insn and B format offset.
Bastian Koppelmann
1
-0
/
+2
2014-12-21
target-tricore: Add missing 1.6 insn of BOL opcode format
Bastian Koppelmann
1
-0
/
+6
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...
Bastian Koppelmann
1
-1
/
+1
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...
Bastian Koppelmann
1
-2
/
+2
2014-12-21
target-tricore: add missing 64-bit MOV in RLC format
Alex Zuepke
1
-0
/
+1
2014-12-21
target-tricore: typo in BOL format
Alex Zuepke
1
-1
/
+1
2014-12-21
target-tricore: fix offset masking in BOL format
Alex Zuepke
1
-1
/
+1
2014-12-10
target-tricore: Add instructions of RCR opcode format
Bastian Koppelmann
1
-1
/
+2
2014-12-10
target-tricore: Add instructions of RLC opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of RC opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of BRR opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of BRN opcode format
Bastian Koppelmann
1
-0
/
+1
2014-12-10
target-tricore: Add instructions of BRC opcode format
Bastian Koppelmann
1
-2
/
+4
2014-12-10
target-tricore: Add instructions of BOL opcode format
Bastian Koppelmann
1
-1
/
+3
2014-10-20
target-tricore: Add instructions of BO opcode format
Bastian Koppelmann
1
-0
/
+2
2014-10-20
target-tricore: Cleanup and Bugfixes
Bastian Koppelmann
1
-1
/
+1
2014-09-01
target-tricore: Add masks and opcodes for decoding
Bastian Koppelmann
1
-0
/
+1406