Age | Commit message (Expand) | Author | Files | Lines |
2008-10-06 | Show size for unassigned accesses (Robert Reif) | blueswir1 | 1 | -1/+1 |
2008-10-03 | Rearrange tick functions | blueswir1 | 1 | -0/+7 |
2008-10-03 | Fix missing prototype warnings by moving declarations | blueswir1 | 1 | -0/+9 |
2008-09-22 | Add software and timer interrupt support | blueswir1 | 1 | -0/+2 |
2008-09-20 | Move signal handler prototype back to cpu.h | blueswir1 | 1 | -0/+1 |
2008-09-10 | Convert rest of ops using float32 to TCG, remove FT0 and FT1 | blueswir1 | 1 | -1/+0 |
2008-09-09 | Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG | blueswir1 | 1 | -16/+5 |
2008-09-06 | Silence gcc warning about constant overflow | blueswir1 | 1 | -1/+9 |
2008-08-29 | Fix FCC handling for Sparc64 target, initial patch by Vince Weaver | blueswir1 | 1 | -26/+26 |
2008-08-29 | Fix Sparc64 boot on i386 host: | blueswir1 | 1 | -6/+32 |
2008-08-21 | Use initial CPU definition structure for some CPU fields instead of copying | blueswir1 | 1 | -39/+49 |
2008-07-25 | Make MAXTL dynamic, bounds check tl when indexing | blueswir1 | 1 | -3/+5 |
2008-07-24 | Sparc32: save/load all MMU registers, Sparc64: add CPU save/load | blueswir1 | 1 | -1/+1 |
2008-07-21 | Use MMU globals for some MMU traps | blueswir1 | 1 | -1/+2 |
2008-07-20 | Make UA200x features selectable, add MMU types | blueswir1 | 1 | -0/+10 |
2008-07-16 | Fix MMU miss traps | blueswir1 | 1 | -2/+2 |
2008-07-01 | Move interrupt_request and user_mode_only to common cpu state. | pbrook | 1 | -2/+0 |
2008-06-30 | Move CPU save/load registration to common code. | pbrook | 1 | -0/+2 |
2008-06-29 | Add instruction counter. | pbrook | 1 | -0/+5 |
2008-06-23 | Fix compiler warning (Jan Kiszka) | blueswir1 | 1 | -1/+2 |
2008-06-07 | Allow NWINDOWS selection (CPU feature with model specific defaults) | blueswir1 | 1 | -6/+27 |
2008-05-30 | Fix typo. | pbrook | 1 | -1/+1 |
2008-05-30 | Move clone() register setup to target specific code. Handle fork-like clone. | pbrook | 1 | -0/+12 |
2008-05-29 | MicroSparc I didn't have fsmuld op | blueswir1 | 1 | -2/+3 |
2008-05-29 | Push common interrupt variables to cpu-defs.h (Glauber Costa) | bellard | 1 | -2/+0 |
2008-05-28 | moved halted field to CPU_COMMON | bellard | 1 | -1/+0 |
2008-05-12 | Wrap long lines | blueswir1 | 1 | -1/+1 |
2008-05-10 | Remove duplicated field | blueswir1 | 1 | -1/+0 |
2008-05-10 | suppressed fixed registers | bellard | 1 | -2/+5 |
2008-05-10 | Fix compiler warnings | blueswir1 | 1 | -7/+7 |
2008-05-09 | CPU feature selection support | blueswir1 | 1 | -3/+27 |
2008-05-04 | Complete the TCG conversion | blueswir1 | 1 | -4/+2 |
2008-04-23 | Document the shift values | blueswir1 | 1 | -6/+12 |
2008-03-29 | Move CPU stuff unrelated to translation to helper.c | blueswir1 | 1 | -0/+1 |
2008-03-16 | Convert mulscc to TCG, add cc_src2 | blueswir1 | 1 | -1/+1 |
2008-03-13 | Convert condition code changing versions of add, sub, logic, and div to TCG | blueswir1 | 1 | -0/+5 |
2008-03-06 | Convert exception ops to TCG | blueswir1 | 1 | -1/+0 |
2008-03-05 | Convert Sparc64 trap state ops to TCG | blueswir1 | 1 | -4/+8 |
2008-03-02 | Convert tick operations to TCG | blueswir1 | 1 | -3/+0 |
2008-02-14 | Fix remote debugger memory access problems reported by Matthias Stein | blueswir1 | 1 | -5/+8 |
2008-02-11 | Sparc32 MMU register fixes (Robert Reif) | blueswir1 | 1 | -0/+4 |
2007-11-28 | Use slavio base as boot prom address, rearrange sun4m init code | blueswir1 | 1 | -0/+1 |
2007-11-25 | 128-bit float support for user mode | blueswir1 | 1 | -0/+3 |
2007-11-25 | More MMU registers (Robert Reif) | blueswir1 | 1 | -1/+1 |
2007-11-10 | added cpu_model parameter to cpu_init() | bellard | 1 | -6/+2 |
2007-11-07 | CPU specific boot mode (Robert Reif) | blueswir1 | 1 | -1/+1 |
2007-10-14 | Sparc64 hypervisor mode | blueswir1 | 1 | -4/+35 |
2007-10-14 | SuperSparc MXCC support (Robert Reif) | blueswir1 | 1 | -1/+4 |
2007-10-14 | Replace is_user variable with mmu_idx in softmmu core, | j_mayer | 1 | -0/+11 |
2007-10-12 | Unify '-cpu ?' option. | j_mayer | 1 | -0/+1 |