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path: root/target-ppc/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2014-06-16spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODEAlexey Kardashevskiy1-1/+3
2014-06-16target-ppc: Add POWER8's Event Based Branch (EBB) control SPRsAlexey Kardashevskiy1-0/+7
2014-06-16KVM: target-ppc: Enable TM state migrationAlexey Kardashevskiy1-0/+14
2014-06-16target-ppc: Add POWER8's TM SPRsAlexey Kardashevskiy1-0/+10
2014-06-16target-ppc: Add POWER8's MMCR2/MMCRS SPRsAlexey Kardashevskiy1-0/+3
2014-06-16target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy1-0/+16
2014-06-16target-ppc: Add POWER8's TIR SPRAlexey Kardashevskiy1-0/+1
2014-06-16target-ppc: Add HID4 SPR for PPC970Alexey Kardashevskiy1-0/+1
2014-06-16target-ppc: Add PMC7/8 to 970 classAlexey Kardashevskiy1-0/+4
2014-06-16target-ppc: Add "POWER" prefix to MMCRA PMU registersAlexey Kardashevskiy1-1/+2
2014-06-16target-ppc: Copy and split gen_spr_7xx() for 970Alexey Kardashevskiy1-0/+20
2014-06-16target-ppc: Merge 970FX and 970MP into a single 970 classAlexey Kardashevskiy1-0/+5
2014-06-16target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRsAlexey Kardashevskiy1-20/+20
2014-06-16PPC: e500: Merge 32 and 64 bit SPE emulationAlexander Graf1-4/+0
2014-06-16spapr: Limit threads per core according to current compatibility modeAlexey Kardashevskiy1-0/+1
2014-06-16target-ppc: Implement "compat" CPU optionAlexey Kardashevskiy1-0/+11
2014-06-16PPC: Properly emulate L1CSR0 and L1CSR1Alexander Graf1-0/+12
2014-06-16PPC: Add L1CFG1 SPR emulationAlexander Graf1-0/+1
2014-06-16PPC: Add definitions for GIVORsAlexander Graf1-0/+6
2014-05-13cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini1-3/+0
2014-04-08PPC: Clean up DECR implementationAlexander Graf1-0/+1
2014-03-20target-ppc: Introduce powerisa-207-server flagAlexey Kardashevskiy1-0/+2
2014-03-20target-ppc: Reset SPRs on CPU resetAlexey Kardashevskiy1-0/+1
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber1-2/+2
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-8/+0
2014-03-05target-ppc: add PowerPCCPU::cpu_dt_idAlexey Kardashevskiy1-0/+18
2014-03-05target-ppc: Fix htab_mask calculationAneesh Kumar K.V1-0/+1
2014-03-05target-ppc: Altivec 2.07: Update AVR StructureTom Musta1-0/+4
2014-03-05target-ppc: Altivec 2.07: Add Instruction FlagTom Musta1-1/+4
2014-03-05target-ppc: Add Load Quadword and ReserveTom Musta1-0/+1
2014-03-05target-ppc: Add Flag for ISA 2.07 Load/Store Quadword InstructionsTom Musta1-1/+3
2014-03-05target-ppc: Add Target Address SPR (TAR) to Power8Tom Musta1-0/+1
2014-03-05target-ppc: Add Flag for bctarTom Musta1-2/+4
2014-03-05target-ppc: Add Flag for Power ISA V2.06 Floating Point Test InstructionsTom Musta1-1/+3
2014-03-05target-ppc: Add Flag for ISA V2.06 Floating Point ConversionTom Musta1-1/+4
2014-03-05target-ppc: Add Flag for ISA2.06 Atomic InstructionsTom Musta1-1/+4
2014-03-05target-ppc: Add Flag for ISA2.06 Divide Extended InstructionsTom Musta1-1/+4
2014-03-05target-ppc: Add ISA2.06 bpermd InstructionTom Musta1-1/+3
2014-03-05target-ppc: VSX Stage 4: Add VSX 2.07 FlagTom Musta1-1/+3
2014-03-05target-ppc: fix SPR_CTRL/SPR_UCTRL register numbersAlexey Kardashevskiy1-2/+2
2014-03-05target-ppc: fix LPCR SPR numberAlexey Kardashevskiy1-1/+1
2013-12-20Add MSR VSX and Associated ExceptionTom Musta1-0/+4
2013-12-20Declare and Enable VSXTom Musta1-1/+4
2013-10-25target-ppc: Use #define for max slb entriesAneesh Kumar K.V1-1/+2
2013-09-02target-ppc: USE LPCR_ILE to control exception endian on POWER7Anton Blanchard1-0/+2
2013-07-29target-ppc: Convert ppc cpu savevm to VMStateDescriptionAlexey Kardashevskiy1-5/+3
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell1-20/+0
2013-07-01target-ppc: Introduce unrealizefn for PowerPCCPUAndreas Färber1-1/+3
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