| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2007-04-13 | Nicer Log formatting. | ths | 1 | -1/+1 |
| 2007-04-13 | Another fix for CP0 Cause register handling. | ths | 2 | -2/+2 |
| 2007-04-11 | Make SYNCI_Step and CCRes CPU-specific. | ths | 2 | -3/+16 |
| 2007-04-11 | Throw RI for invalid MFMC0-class instructions. Introduce optional | ths | 2 | -3/+18 |
| 2007-04-11 | Code formatting fix. | ths | 1 | -935/+938 |
| 2007-04-11 | More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may | ths | 2 | -10/+10 |
| 2007-04-09 | Fix CP0_IntCtl handling. | ths | 2 | -2/+6 |
| 2007-04-09 | Proper handling of reserved bits in the context register. | ths | 1 | -1/+1 |
| 2007-04-09 | Mark watchpoint features as unimplemented. | ths | 2 | -3/+9 |
| 2007-04-09 | Catch unaligned sc/scd. | ths | 2 | -0/+10 |
| 2007-04-09 | Fix exception handling cornercase for rdhwr. | ths | 2 | -37/+9 |
| 2007-04-09 | Remove bogus mtc0 handling. | ths | 1 | -10/+0 |
| 2007-04-07 | Unify IRQ handling. | pbrook | 1 | -0/+2 |
| 2007-04-07 | cpu_get_phys_page_debug should return target_phys_addr_t | j_mayer | 1 | -2/+2 |
| 2007-04-07 | Implement prefx. | ths | 1 | -1/+41 |
| 2007-04-07 | Set proper BadVAddress value for unaligned instruction fetch. | ths | 1 | -1/+2 |
| 2007-04-07 | Actually skip over delay slot for a non-taken branch likely. | ths | 1 | -2/+2 |
| 2007-04-07 | Fix ins/ext cornercase. | ths | 1 | -4/+4 |
| 2007-04-06 | Fix handling of ADES exceptions. | ths | 1 | -1/+3 |
| 2007-04-06 | Save state for all CP0 instructions, they may throw a CPU exception. | ths | 3 | -16/+45 |
| 2007-04-05 | fix branch delay slot cornercases. | ths | 2 | -3/+6 |
| 2007-04-05 | Fix rotr immediate ops, mask shift/rotate arguments to their allowed | ths | 3 | -48/+103 |
| 2007-04-05 | Handle EBase properly. | ths | 1 | -1/+1 |
| 2007-04-05 | Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise | ths | 2 | -92/+131 |
| 2007-04-05 | 64bit MIPS FPUs have 32 registers. | ths | 1 | -2/+1 |
| 2007-04-04 | Fix code formatting. | ths | 1 | -66/+66 |
| 2007-04-02 | MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers | ths | 1 | -2/+9 |
| 2007-04-02 | Build fix for 64bit machines. (This is still not correct mul/div handling.) | ths | 1 | -6/+12 |
| 2007-04-01 | Actually enable 64bit configuration. | ths | 8 | -38/+35 |
| 2007-04-01 | MIPS64 configurations. | ths | 1 | -2/+0 |
| 2007-03-31 | Malta CBUS UART support. | ths | 1 | -1/+1 |
| 2007-03-30 | Update mips TODO. | ths | 1 | -5/+1 |
| 2007-03-30 | Fix typo, suggested by Ben Taylor. | ths | 1 | -1/+1 |
| 2007-03-30 | Squash logic bugs while they are fresh... | ths | 1 | -1/+0 |
| 2007-03-30 | Sanitize mips exception handling. | ths | 5 | -73/+55 |
| 2007-03-24 | One more bit of mips CPU configuration, and support for early 4KEc | ths | 1 | -1/+23 |
| 2007-03-23 | Fix enough FPU/R2 support to get 24Kf going. | ths | 5 | -26/+66 |
| 2007-03-21 | Move mips CPU specific initialization to translate_init.c. | ths | 3 | -40/+61 |
| 2007-03-19 | Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil. | ths | 1 | -5/+13 |
| 2007-03-19 | Define gen_intermediate_code_internal as "static inline". | ths | 1 | -2/+3 |
| 2007-03-19 | SPARC host fixes, by Ben Taylor. | ths | 1 | -10/+0 |
| 2007-03-18 | Fix BD flag handling, cause register contents, implement some more bits | ths | 2 | -4/+17 |
| 2007-03-18 | MIPS -cpu selection support, by Herve Poussineau. | ths | 4 | -33/+104 |
| 2007-03-17 | Note FPU enable/disable issue. | ths | 1 | -0/+2 |
| 2007-03-02 | MIPS Userland TLS register emulation, by Daniel Jacobowitz. | ths | 3 | -0/+17 |
| 2007-02-28 | MIPS FPU dynamic activation, part 1, by Herve Poussineau. | ths | 7 | -101/+65 |
| 2007-02-27 | Fix mips FPU emulation, 32 bit data types are allowed to use odd registers. | ths | 2 | -30/+17 |
| 2007-02-20 | Replace TLSZ with TARGET_FMT_lx. | ths | 5 | -43/+36 |
| 2007-02-18 | Fix sign-extension of VPN field in TLB, by Herve Poussineau. | ths | 3 | -3/+3 |
| 2007-02-02 | Update MIPS TODO. | ths | 1 | -4/+2 |
