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2007-04-29Kill broken host register definitions, thanks to Paul Brook and Herveths2-13/+4
2007-04-29Revert last checkin.ths1-1/+1
2007-04-29Hopefully the final fix for LUI sign extensions.ths1-1/+1
2007-04-28Update TODO.ths1-0/+9
2007-04-25Next attempt to get the lui sign extension right.ths2-3/+2
2007-04-25Fix lui sign extension.ths1-1/+1
2007-04-19Update comment. We can't easily adhere to the architecture spec becauseths1-3/+3
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths6-26/+25
2007-04-16Simplify branch likely handling.ths1-6/+8
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths2-6/+6
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths3-13/+28
2007-04-15Small code generation optimization.ths1-3/+6
2007-04-15Delete unused define.ths1-2/+0
2007-04-14Restart interrupts after an exception.ths2-9/+33
2007-04-13Nicer Log formatting.ths1-1/+1
2007-04-13Another fix for CP0 Cause register handling.ths2-2/+2
2007-04-11Make SYNCI_Step and CCRes CPU-specific.ths2-3/+16
2007-04-11Throw RI for invalid MFMC0-class instructions. Introduce optionalths2-3/+18
2007-04-11Code formatting fix.ths1-935/+938
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths2-10/+10
2007-04-09Fix CP0_IntCtl handling.ths2-2/+6
2007-04-09Proper handling of reserved bits in the context register.ths1-1/+1
2007-04-09Mark watchpoint features as unimplemented.ths2-3/+9
2007-04-09Catch unaligned sc/scd.ths2-0/+10
2007-04-09Fix exception handling cornercase for rdhwr.ths2-37/+9
2007-04-09Remove bogus mtc0 handling.ths1-10/+0
2007-04-07Unify IRQ handling.pbrook1-0/+2
2007-04-07cpu_get_phys_page_debug should return target_phys_addr_tj_mayer1-2/+2
2007-04-07Implement prefx.ths1-1/+41
2007-04-07Set proper BadVAddress value for unaligned instruction fetch.ths1-1/+2
2007-04-07Actually skip over delay slot for a non-taken branch likely.ths1-2/+2
2007-04-07Fix ins/ext cornercase.ths1-4/+4
2007-04-06Fix handling of ADES exceptions.ths1-1/+3
2007-04-06Save state for all CP0 instructions, they may throw a CPU exception.ths3-16/+45
2007-04-05fix branch delay slot cornercases.ths2-3/+6
2007-04-05Fix rotr immediate ops, mask shift/rotate arguments to their allowedths3-48/+103
2007-04-05Handle EBase properly.ths1-1/+1
2007-04-05Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths2-92/+131
2007-04-0564bit MIPS FPUs have 32 registers.ths1-2/+1
2007-04-04Fix code formatting.ths1-66/+66
2007-04-02MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registersths1-2/+9
2007-04-02Build fix for 64bit machines. (This is still not correct mul/div handling.)ths1-6/+12
2007-04-01Actually enable 64bit configuration.ths8-38/+35
2007-04-01MIPS64 configurations.ths1-2/+0
2007-03-31Malta CBUS UART support.ths1-1/+1
2007-03-30Update mips TODO.ths1-5/+1
2007-03-30Fix typo, suggested by Ben Taylor.ths1-1/+1
2007-03-30Squash logic bugs while they are fresh...ths1-1/+0
2007-03-30Sanitize mips exception handling.ths5-73/+55
2007-03-24One more bit of mips CPU configuration, and support for early 4KEcths1-1/+23
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