index
:
sdk/emulator/qemu
1.0_post
2.0alpha
features/brillcodec_2i
features/camera
features/cnp
features/dr
features/qt_dr
features/smp
features/virtio-9p
features/vmodem
glesv3
master
opensrc_p2.3
opensrc_p2.3.1
opensrc_p2.3.2
opensrc_p2.4
opensrc_p3.0
opensrc_p4.0
sandbox/byungchul.so/tizen
sandbox/elebideau/tizen
sandbox/mmajewski2/maru-virgl-rendering-wip
sandbox/mmajewski2/standalone-virgl-wip
sandbox/pcoval/tizen
spin
tizen
tizen_2.0
tizen_2.1
tizen_2.2
tizen_3.0.m14.4_ivi
tizen_p2.3
tizen_p2.3.1
tizen_qemu_1.6
tizen_qemu_1.7
tizen_qemu_2.0
tizen_qemu_5.0.1
tizen_studio_1.2_p2.3
tizen_studio_1.2_p2.3.1
tizen_studio_1.2_p2.3.2
tizen_studio_1.2_p2.4
tizen_studio_1.2_p3.0
tizen_studio_1.3_p2.3
tizen_studio_1.3_p2.3.1
tizen_studio_1.3_p2.3.2
tizen_studio_1.3_p2.4
tizen_studio_1.3_p3.0
tizen_studio_2.0_p2.3
tizen_studio_2.0_p2.3.1
tizen_studio_2.0_p2.3.2
tizen_studio_2.0_p2.4
tizen_studio_2.0_p3.0
tizen_studio_2.0_p4.0
tizen_studio_2.0_p5.0
tizen_studio_3.0_p2.3
tizen_studio_3.0_p2.3.1
tizen_studio_3.0_p2.3.2
tizen_studio_3.0_p2.4
tizen_studio_3.0_p3.0
tizen_studio_3.0_p4.0
tizen_studio_3.0_p5.0
tizen_studio_3.5_p2.3
tizen_studio_3.5_p2.3.1
tizen_studio_3.5_p2.3.2
tizen_studio_3.5_p2.4
tizen_studio_3.5_p3.0
tizen_studio_3.5_p4.0
tizen_studio_3.5_p5.0
tizen_studio_3.5_p5.5
tizen_studio_4.0_p2.3
tizen_studio_4.0_p2.3.1
tizen_studio_4.0_p2.3.2
tizen_studio_4.0_p2.4
tizen_studio_4.0_p3.0
tizen_studio_4.0_p4.0
tizen_studio_4.0_p5.0
tizen_studio_4.0_p5.5
tizen_studio_4.0_p6.0
tizen_studio_4.5_p6.5
tizen_studio_5.0_p7.0
tizen_studio_5.5_p7.5
tizen_studio_5.5_p8.0
tizen_studio_6.0_p9.0
tizen_studio_p2.3
tizen_studio_p2.3.1
tizen_studio_p2.3.2
tizen_studio_p2.4
tizen_studio_p3.0
tizen_studio_p4.0
works/arg_renewal
Domain: SDK / Emulator;
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-mips
Age
Commit message (
Expand
)
Author
Files
Lines
2008-09-21
Add concat_i32_i64 op.
pbrook
1
-17
/
+6
2008-09-18
Use TCG registers for most CPU register accesses.
ths
1
-17
/
+52
2008-09-18
Move the active FPU registers into env again, and use more TCG registers
ths
6
-314
/
+330
2008-09-14
MIPS: Fix tlbwi/tlbwr
aurel32
1
-3
/
+9
2008-09-14
MIPS: remove empty cpu_mips_irqctrl_init()
aurel32
1
-1
/
+0
2008-09-14
target-mips: fix warning
aurel32
1
-1
/
+1
2008-09-05
TCG fixes for target-mips
aurel32
1
-26
/
+27
2008-09-02
Build fix for gcc-3.3.
ths
1
-0
/
+4
2008-08-30
Fix some warnings that would be generated by gcc -Wredundant-decls
blueswir1
1
-3
/
+0
2008-08-23
MIPS: don't free TCG temporary variable twice
aurel32
1
-2
/
+0
2008-08-01
Delete unused variable.
ths
1
-1
/
+0
2008-07-23
Use plain standard inline.
ths
2
-11
/
+11
2008-07-23
Less hardcoding of TARGET_USER_ONLY.
ths
6
-390
/
+287
2008-07-21
A bunch of minor code improvements in the MIPS target.
ths
2
-21
/
+10
2008-07-21
Fix logging output for MIPS HI, LO registers, by Stefan Weil.
ths
1
-1
/
+2
2008-07-20
Fix compiler warning, by Stefan Weil.
ths
1
-1
/
+1
2008-07-20
Simplify conditional FP moves.
ths
1
-10
/
+5
2008-07-18
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
ths
1
-7
/
+5
2008-07-09
Use temporary registers for the MIPS FPU emulation.
ths
5
-984
/
+1849
2008-07-05
Fix typo in comment.
ths
1
-1
/
+1
2008-07-05
Change MIPS machine default to Malta.
ths
1
-2
/
+2
2008-07-01
Move interrupt_request and user_mode_only to common cpu state.
pbrook
1
-2
/
+0
2008-07-01
Static'ify some functions, and use standard inline in translate.c.
ths
1
-22
/
+22
2008-07-01
Delete duplicate code.
ths
1
-3
/
+0
2008-06-30
Spelling fixes, spotted by Stuart Brady.
ths
1
-2
/
+2
2008-06-30
Move CPU save/load registration to common code.
pbrook
1
-0
/
+2
2008-06-30
Make bcond and btarget TCG registers.
ths
1
-73
/
+43
2008-06-29
Remove unnecessary helper arguments, and fix some typos.
ths
3
-21
/
+31
2008-06-29
Add missing file. Fix spelling errors.
pbrook
1
-1
/
+0
2008-06-29
Add instruction counter.
pbrook
2
-0
/
+57
2008-06-27
Avoid unused input arguments which triggered tcg errors. Spotted by
ths
3
-28
/
+30
2008-06-27
More efficient target register / TC accesses.
ths
5
-197
/
+278
2008-06-24
Clarify some TODO items.
ths
1
-4
/
+5
2008-06-24
Remove remaining uses of T0 in the MIPS target.
ths
5
-454
/
+468
2008-06-24
T1 is now dead.
ths
3
-7
/
+1
2008-06-24
Reduce use of fixed registers a bit more.
ths
1
-329
/
+356
2008-06-24
Use temporaries instead of fixed registers for some instructions.
ths
3
-303
/
+408
2008-06-23
Pass T0/T1 explicitly to helper functions, and clean up a few dyngen
ths
4
-1105
/
+1130
2008-06-20
Delete obsolete file.
ths
1
-21
/
+0
2008-06-20
Delete obsolete file.
ths
1
-269
/
+0
2008-06-20
Delete obsolete prototypes.
ths
1
-21
/
+0
2008-06-20
Convert unaligned load/store to TCG.
ths
4
-65
/
+364
2008-06-20
Convert vr54xx multiply instructions to TCG.
ths
4
-240
/
+32
2008-06-19
Remove now-dead code.
ths
1
-27
/
+0
2008-06-19
Convert remaining MIPS FP instructions to TCG.
ths
4
-363
/
+426
2008-06-12
Switch the standard multiplication instructions to TCG.
ths
5
-94
/
+166
2008-06-12
Switch bitfield instructions and assorted special ops to TCG.
ths
4
-195
/
+189
2008-06-12
TCGify the simplest FP instructions.
ths
3
-52
/
+14
2008-06-12
TCGify a few more instructions.
ths
5
-89
/
+38
2008-06-11
Update TODO list.
ths
1
-0
/
+5
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