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2016-02-15target-i386: Implement FSGSBASERichard Henderson1-0/+34
2016-02-15target-i386: Clear bndregs during legacy near jumpsRichard Henderson1-0/+20
2016-02-15target-i386: Implement BNDLDX, BNDSTXRichard Henderson1-0/+57
2016-02-15target-i386: Implement BNDCL, BNDCU, BNDCNRichard Henderson1-1/+43
2016-02-15target-i386: Implement BNDMOVRichard Henderson1-1/+72
2016-02-15target-i386: Implement BNDMKRichard Henderson1-1/+57
2016-02-13target-i386: Split up gen_lea_modrmRichard Henderson1-114/+85
2016-02-13target-i386: Perform set/reset_inhibit_irq inlineRichard Henderson1-9/+28
2016-02-13target-i386: Enable control registers for MPXRichard Henderson1-0/+5
2016-02-13target-i386: Implement XSAVEOPTRichard Henderson1-3/+15
2016-02-13target-i386: Add XSAVE extensionRichard Henderson1-0/+54
2016-02-13target-i386: Rearrange processing of 0F AERichard Henderson1-52/+72
2016-02-13target-i386: Rearrange processing of 0F 01Richard Henderson1-223/+247
2016-02-13target-i386: Split fxsave/fxrstor implementationRichard Henderson1-2/+2
2016-02-09target-i386: Deconstruct the cpu_T arrayRichard Henderson1-607/+617
2016-02-09target-i386: Tidy gen_add_A0_imRichard Henderson1-22/+5
2016-02-09target-i386: Rewrite leaveRichard Henderson1-14/+15
2016-02-09target-i386: Rewrite gen_enter inlineRichard Henderson1-59/+34
2016-02-09target-i386: Use gen_lea_v_seg in pusha/popaRichard Henderson1-27/+23
2016-02-09target-i386: Access segs via TCG registersRichard Henderson1-24/+28
2016-02-09target-i386: Use gen_lea_v_seg in stack subroutinesRichard Henderson1-39/+13
2016-02-09target-i386: Use gen_lea_v_seg in gen_lea_modrmRichard Henderson1-59/+23
2016-02-09target-i386: Introduce mo_stacksizeRichard Henderson1-14/+10
2016-02-09target-i386: Create gen_lea_v_segRichard Henderson1-107/+53
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson1-5/+5
2016-02-09tcg: Remove lingering references to gen_opc_bufRichard Henderson1-2/+1
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini1-0/+1
2016-01-29x86: Clean up includesPeter Maydell1-5/+1
2016-01-21target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*Eduardo Habkost1-94/+94
2016-01-21target-i386: Rename struct XMMReg to ZMMRegEduardo Habkost1-11/+11
2016-01-21target-i386: Rename optimize_flags_init()Eduardo Habkost1-1/+1
2015-11-17target-i386: Fix mulx for identical target regsRichard Henderson1-1/+3
2015-11-06target-i386: tcg: Check right CPUID bits for clflushopt/pcommitEduardo Habkost1-8/+20
2015-11-06target-i386: tcg: Accept clwb instructionEduardo Habkost1-1/+12
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-0/+5
2015-10-27target-i386: Don't left shift negative constantEduardo Habkost1-1/+1
2015-10-23target-i386: Check CR4[DE] for processing DR4/DR5Richard Henderson1-4/+6
2015-10-23target-i386: Handle I/O breakpointsEduardo Habkost1-1/+19
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-44/+5
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-20/+6
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-1/+5
2015-10-07target-i386: Add cc_op state to insn_startRichard Henderson1-1/+1
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-10/+7
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+3
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-3/+2
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-15target-i386: exception handling for seg_helper functionsPavel Dovgalyuk1-33/+9
2015-09-15target-i386: exception handling for memory helpersPavel Dovgalyuk1-5/+0
2015-09-15target-i386: exception handling for div instructionsPavel Dovgalyuk1-8/+0
2015-09-15target-i386: exception handling for FPU instructionsPavel Dovgalyuk1-24/+0
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