index
:
sdk/emulator/qemu
1.0_post
2.0alpha
features/brillcodec_2i
features/camera
features/cnp
features/dr
features/qt_dr
features/smp
features/virtio-9p
features/vmodem
glesv3
master
opensrc_p2.3
opensrc_p2.3.1
opensrc_p2.3.2
opensrc_p2.4
opensrc_p3.0
opensrc_p4.0
sandbox/byungchul.so/tizen
sandbox/elebideau/tizen
sandbox/mmajewski2/maru-virgl-rendering-wip
sandbox/mmajewski2/standalone-virgl-wip
sandbox/pcoval/tizen
spin
tizen
tizen_2.0
tizen_2.1
tizen_2.2
tizen_3.0.m14.4_ivi
tizen_p2.3
tizen_p2.3.1
tizen_qemu_1.6
tizen_qemu_1.7
tizen_qemu_2.0
tizen_qemu_5.0.1
tizen_studio_1.2_p2.3
tizen_studio_1.2_p2.3.1
tizen_studio_1.2_p2.3.2
tizen_studio_1.2_p2.4
tizen_studio_1.2_p3.0
tizen_studio_1.3_p2.3
tizen_studio_1.3_p2.3.1
tizen_studio_1.3_p2.3.2
tizen_studio_1.3_p2.4
tizen_studio_1.3_p3.0
tizen_studio_2.0_p2.3
tizen_studio_2.0_p2.3.1
tizen_studio_2.0_p2.3.2
tizen_studio_2.0_p2.4
tizen_studio_2.0_p3.0
tizen_studio_2.0_p4.0
tizen_studio_2.0_p5.0
tizen_studio_3.0_p2.3
tizen_studio_3.0_p2.3.1
tizen_studio_3.0_p2.3.2
tizen_studio_3.0_p2.4
tizen_studio_3.0_p3.0
tizen_studio_3.0_p4.0
tizen_studio_3.0_p5.0
tizen_studio_3.5_p2.3
tizen_studio_3.5_p2.3.1
tizen_studio_3.5_p2.3.2
tizen_studio_3.5_p2.4
tizen_studio_3.5_p3.0
tizen_studio_3.5_p4.0
tizen_studio_3.5_p5.0
tizen_studio_3.5_p5.5
tizen_studio_4.0_p2.3
tizen_studio_4.0_p2.3.1
tizen_studio_4.0_p2.3.2
tizen_studio_4.0_p2.4
tizen_studio_4.0_p3.0
tizen_studio_4.0_p4.0
tizen_studio_4.0_p5.0
tizen_studio_4.0_p5.5
tizen_studio_4.0_p6.0
tizen_studio_4.5_p6.5
tizen_studio_5.0_p7.0
tizen_studio_5.5_p7.5
tizen_studio_5.5_p8.0
tizen_studio_6.0_p9.0
tizen_studio_p2.3
tizen_studio_p2.3.1
tizen_studio_p2.3.2
tizen_studio_p2.4
tizen_studio_p3.0
tizen_studio_p4.0
works/arg_renewal
Domain: SDK / Emulator;
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-cris
/
translate.c
Age
Commit message (
Expand
)
Author
Files
Lines
2016-06-20
exec: [tcg] Track which vCPU is performing translation and execution
Lluís Vilanova
1
-0
/
+1
2016-06-05
target-*: dfilter support for in_asm
Richard Henderson
1
-1
/
+2
2016-05-19
cpu: move exec-all.h inclusion out of cpu.h
Paolo Bonzini
1
-0
/
+1
2016-05-18
Fix some typos found by codespell
Stefan Weil
1
-2
/
+2
2016-05-12
tcg: Allow goto_tb to any target PC in user mode
Sergey Fedorov
1
-6
/
+12
2016-05-12
tcg: Clean up direct block chaining safety checks
Sergey Fedorov
1
-1
/
+3
2016-03-01
tcg: Add type for vCPU pointers
Lluís Vilanova
1
-1
/
+1
2016-02-09
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
Richard Henderson
1
-12
/
+12
2016-02-03
log: do not unnecessarily include qom/cpu.h
Paolo Bonzini
1
-0
/
+1
2016-01-29
cris: Clean up includes
Peter Maydell
1
-0
/
+1
2015-12-17
cris: avoid "naked" qemu_log
Paolo Bonzini
1
-1
/
+1
2015-12-17
qemu-log: introduce qemu_log_separate
Paolo Bonzini
1
-2
/
+4
2015-10-28
target-*: Advance pc after recognizing a breakpoint
Richard Henderson
1
-0
/
+5
2015-10-07
tcg: Remove gen_intermediate_code_pc
Richard Henderson
1
-44
/
+6
2015-10-07
tcg: Pass data argument to restore_state_to_opc
Richard Henderson
1
-2
/
+3
2015-10-07
tcg: Add TCG_MAX_INSNS
Richard Henderson
1
-0
/
+3
2015-10-07
target-cris: Mirror gen_opc_pc into insn_start
Richard Henderson
1
-1
/
+2
2015-10-07
target-*: Introduce and use cpu_breakpoint_test
Richard Henderson
1
-19
/
+8
2015-10-07
target-*: Increment num_insns immediately after tcg_gen_insn_start
Richard Henderson
1
-2
/
+2
2015-10-07
target-*: Unconditionally emit tcg_gen_insn_start
Richard Henderson
1
-4
/
+1
2015-10-07
tcg: Rename debug_insn_start to insn_start
Richard Henderson
1
-2
/
+2
2015-09-11
tlb: Add "ifetch" argument to cpu_mmu_index()
Benjamin Herrenschmidt
1
-3
/
+3
2015-09-11
typofixes - v4
Veres Lajos
1
-3
/
+3
2015-09-08
target-cris: Use movcond and setcond
Richard Henderson
1
-20
/
+7
2015-08-24
tcg: Remove tcg_gen_trunc_i64_i32
Richard Henderson
1
-2
/
+2
2015-06-22
disas: Remove uses of CPU env
Peter Crosthwaite
1
-1
/
+1
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
1
-17
/
+6
2015-02-12
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
Richard Henderson
1
-8
/
+5
2015-02-12
tcg: Move emit of INDEX_op_end into gen_tb_end
Richard Henderson
1
-1
/
+1
2015-01-03
gen-icount: check cflags instead of use_icount global
Paolo Bonzini
1
-1
/
+1
2014-11-17
target-cris/translate.c: fix out of bounds read
zhanghailiang
1
-6
/
+2
2014-08-12
trace: [tcg] Include TCG-tracing header on all targets
Lluís Vilanova
1
-0
/
+3
2014-06-09
target-cris/translate.c: Remove _t_gen_mov_TN_env and _t_gen_mov_env_TN
Peter Maydell
1
-17
/
+2
2014-06-09
target-cris/translate.c: Remove t_gen_mov_TN_reg and t_gen_mov_reg_TN
Peter Maydell
1
-18
/
+3
2014-06-05
softmmu: introduce cpu_ldst.h
Paolo Bonzini
1
-0
/
+1
2014-05-28
tcg: Invert the inclusion of helper.h
Richard Henderson
1
-3
/
+2
2014-03-13
target-cris: Replace DisasContext::env field with CRISCPU
Andreas Färber
1
-8
/
+8
2014-03-13
exec: Change cpu_abort() argument to CPUState
Andreas Färber
1
-2
/
+2
2014-03-13
cpu: Move breakpoints field from CPU_COMMON to CPUState
Andreas Färber
1
-2
/
+3
2013-12-08
target-cris: Use new qemu_ld/st opcodes
Richard Henderson
1
-25
/
+4
2013-10-10
tcg: Move helper registration into tcg_context_init
Richard Henderson
1
-3
/
+0
2013-09-02
tcg: Change tcg_gen_exit_tb argument to uintptr_t
Richard Henderson
1
-1
/
+1
2013-07-23
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Andreas Färber
1
-3
/
+4
2013-07-09
target-cris: Change gen_intermediate_code_internal() argument to CRISCPU
Andreas Färber
1
-4
/
+5
2013-07-09
target-cris: gen_intermediate_code_internal() should be inlined
Andreas Färber
1
-1
/
+1
2013-06-28
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Andreas Färber
1
-2
/
+4
2013-03-12
cpu: Move halted and interrupt_request fields to CPUState
Andreas Färber
1
-1
/
+2
2013-03-03
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
Peter Maydell
1
-2
/
+2
2013-02-23
target-cris: Use mul*2 in mul* insns
Richard Henderson
1
-42
/
+2
2013-02-23
qemu-log: Remove qemu_log_try_set_file() and its users
Peter Maydell
1
-2
/
+0
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