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AgeCommit message (Expand)AuthorFilesLines
2012-10-05target-arm: Drop unused DECODE_CPREG_CRN macroPeter Maydell1-2/+0
2012-10-05target-arm: use deposit instead of hardcoded versionAurelien Jarno1-14/+6
2012-10-05target-arm: mark a few integer helpers const and pureAurelien Jarno1-9/+10
2012-10-05target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno3-33/+43
2012-10-05target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno3-40/+48
2012-10-05target-arm: use globals for CC flagsAurelien Jarno1-81/+46
2012-10-05target-arm: Reinstate display of VFP registers in cpu_dump_statePeter Maydell1-26/+16
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-09-15target-arm: final conversion to AREG0 free modeBlue Swirl5-20/+15
2012-09-15target-arm: convert remaining helpersBlue Swirl3-125/+125
2012-09-15target-arm: convert void helpersBlue Swirl3-18/+18
2012-09-10target-arm: Fix potential buffer overflowStefan Weil1-2/+2
2012-08-22arm-semi: don't leak 1KB user string lock buffer upon TARGET_SYS_OPENJim Meyering1-6/+7
2012-08-10target-arm: Fix typos in commentsPeter Maydell6-24/+24
2012-08-10arm: translate: comment typo - s/middel/middle/Peter A. G. Crosthwaite1-1/+1
2012-07-12target-arm: Add support for long format translation table walksPeter Maydell1-0/+182
2012-07-12target-arm: Implement TTBCR changes for LPAEPeter Maydell1-1/+14
2012-07-12target-arm: Implement long-descriptor PAR formatPeter Maydell1-10/+69
2012-07-12target-arm: Use target_phys_addr_t in get_phys_addr()Peter Maydell1-14/+15
2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell3-3/+87
2012-07-12target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAEPeter Maydell1-0/+5
2012-07-12target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registersPeter Maydell1-0/+16
2012-07-12target-arm: Extend feature flags to 64 bitsPeter Maydell3-6/+6
2012-07-12target-arm: Implement privileged-execute-never (PXN)Peter Maydell3-12/+26
2012-07-12ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bitsPeter Maydell1-1/+1
2012-07-12target-arm: Fix TCG temp handling in 64 bit cp writesPeter Maydell1-0/+2
2012-07-12target-arm: Fix some copy-and-paste errors in cp register namesPeter Maydell1-3/+3
2012-07-12target-arm: Fix typo that meant TTBR1 accesses went to TTBR0Peter Maydell1-1/+1
2012-07-12target-arm: Fix CP15 based WFIPaul Brook1-1/+1
2012-06-20target-arm: Remove ARM_CPUID_* macrosPeter Maydell2-52/+25
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell3-100/+1
2012-06-20target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2-6/+14
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell2-4/+1
2012-06-20target-arm: Convert final ID registersPeter Maydell2-50/+68
2012-06-20target-arm: Convert MPIDRPeter Maydell3-22/+31
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell3-32/+33
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell3-24/+54
2012-06-20target-arm: Convert cp15 crn=1 registersPeter Maydell3-76/+61
2012-06-20target-arm: Convert cp15 crn=9 registersPeter Maydell2-79/+59
2012-06-20target-arm: Convert cp15 crn=6 registersPeter Maydell2-53/+45
2012-06-20target-arm: convert cp15 crn=7 registersPeter Maydell3-11/+74
2012-06-20target-arm: Convert cp15 VA-PA translation registersPeter Maydell1-43/+65
2012-06-20target-arm: Convert cp15 MMU TLB controlPeter Maydell1-20/+43
2012-06-20target-arm: Convert cp15 crn=15 registersPeter Maydell3-117/+126
2012-06-20target-arm: Convert cp15 crn=10 registersPeter Maydell1-6/+5
2012-06-20target-arm: Convert cp15 crn=13 registersPeter Maydell1-30/+31
2012-06-20target-arm: Convert cp15 crn=2 registersPeter Maydell2-56/+33
2012-06-20target-arm: Convert MMU fault status cp15 registersPeter Maydell1-81/+107
2012-06-20target-arm: Convert cp15 c3 registerPeter Maydell1-6/+12
2012-06-20target-arm: Convert generic timer cp15 regsPeter Maydell1-12/+11
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