index
:
sdk/emulator/qemu
1.0_post
2.0alpha
features/brillcodec_2i
features/camera
features/cnp
features/dr
features/qt_dr
features/smp
features/virtio-9p
features/vmodem
glesv3
master
opensrc_p2.3
opensrc_p2.3.1
opensrc_p2.3.2
opensrc_p2.4
opensrc_p3.0
opensrc_p4.0
sandbox/byungchul.so/tizen
sandbox/elebideau/tizen
sandbox/mmajewski2/maru-virgl-rendering-wip
sandbox/mmajewski2/standalone-virgl-wip
sandbox/pcoval/tizen
spin
tizen
tizen_2.0
tizen_2.1
tizen_2.2
tizen_3.0.m14.4_ivi
tizen_p2.3
tizen_p2.3.1
tizen_qemu_1.6
tizen_qemu_1.7
tizen_qemu_2.0
tizen_qemu_5.0.1
tizen_studio_1.2_p2.3
tizen_studio_1.2_p2.3.1
tizen_studio_1.2_p2.3.2
tizen_studio_1.2_p2.4
tizen_studio_1.2_p3.0
tizen_studio_1.3_p2.3
tizen_studio_1.3_p2.3.1
tizen_studio_1.3_p2.3.2
tizen_studio_1.3_p2.4
tizen_studio_1.3_p3.0
tizen_studio_2.0_p2.3
tizen_studio_2.0_p2.3.1
tizen_studio_2.0_p2.3.2
tizen_studio_2.0_p2.4
tizen_studio_2.0_p3.0
tizen_studio_2.0_p4.0
tizen_studio_2.0_p5.0
tizen_studio_3.0_p2.3
tizen_studio_3.0_p2.3.1
tizen_studio_3.0_p2.3.2
tizen_studio_3.0_p2.4
tizen_studio_3.0_p3.0
tizen_studio_3.0_p4.0
tizen_studio_3.0_p5.0
tizen_studio_3.5_p2.3
tizen_studio_3.5_p2.3.1
tizen_studio_3.5_p2.3.2
tizen_studio_3.5_p2.4
tizen_studio_3.5_p3.0
tizen_studio_3.5_p4.0
tizen_studio_3.5_p5.0
tizen_studio_3.5_p5.5
tizen_studio_4.0_p2.3
tizen_studio_4.0_p2.3.1
tizen_studio_4.0_p2.3.2
tizen_studio_4.0_p2.4
tizen_studio_4.0_p3.0
tizen_studio_4.0_p4.0
tizen_studio_4.0_p5.0
tizen_studio_4.0_p5.5
tizen_studio_4.0_p6.0
tizen_studio_4.5_p6.5
tizen_studio_5.0_p7.0
tizen_studio_5.5_p7.5
tizen_studio_5.5_p8.0
tizen_studio_6.0_p9.0
tizen_studio_p2.3
tizen_studio_p2.3.1
tizen_studio_p2.3.2
tizen_studio_p2.4
tizen_studio_p3.0
tizen_studio_p4.0
works/arg_renewal
Domain: SDK / Emulator;
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
Age
Commit message (
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)
Author
Files
Lines
2014-03-17
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
Alex Bennée
4
-37
/
+140
2014-03-17
target-arm: A64: Implement FCVTXN
Peter Maydell
3
-1
/
+43
2014-03-17
target-arm: A64: Implement scalar saturating narrow ops
Alex Bennée
1
-7
/
+28
2014-03-17
target-arm: A64: Move handle_2misc_narrow function
Alex Bennée
1
-90
/
+90
2014-03-17
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
Alex Bennée
4
-42
/
+195
2014-03-17
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
Peter Maydell
1
-2
/
+78
2014-03-17
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
Peter Maydell
1
-0
/
+132
2014-03-17
target-arm: A64: Implement FRINT*
Peter Maydell
1
-3
/
+42
2014-03-17
target-arm: A64: Implement SRI
Peter Maydell
1
-8
/
+49
2014-03-17
target-arm: A64: Add FRECPX (reciprocal exponent)
Alex Bennée
3
-1
/
+130
2014-03-17
target-arm: A64: List unsupported shift-imm opcodes
Peter Maydell
1
-2
/
+11
2014-03-17
target-arm: A64: Implement FCVTL
Peter Maydell
1
-0
/
+47
2014-03-17
target-arm: A64: Implement FCVTN
Peter Maydell
1
-1
/
+23
2014-03-17
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
Peter Maydell
1
-19
/
+169
2014-03-17
target-arm: A64: Implement SHLL, SHLL2
Peter Maydell
1
-1
/
+31
2014-03-17
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
Peter Maydell
3
-1
/
+139
2014-03-17
target-arm: A64: Saturating and narrowing shift ops
Alex Bennée
1
-3
/
+178
2014-03-17
target-arm: A64: Add remaining CLS/Z vector ops
Alex Bennée
3
-1
/
+41
2014-03-17
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
Alex Bennée
1
-1
/
+12
2014-03-17
target-arm: A64: Add last AdvSIMD Integer to FP ops
Alex Bennée
1
-9
/
+123
2014-03-17
target-arm: A64: Fix bug in add_sub_ext handling of rn
Alex Bennée
1
-2
/
+1
2014-03-17
target-arm: A64: Implement PMULL instruction
Peter Maydell
5
-2
/
+78
2014-03-17
target-arm: Add ARM_CP_IO notation to PMCR reginfo
Peter Maydell
1
-0
/
+1
2014-03-15
misc: Fix typos in comments
Stefan Weil
1
-1
/
+1
2014-03-13
cputlb: Change tlb_set_page() argument to CPUState
Andreas Färber
1
-1
/
+1
2014-03-13
cputlb: Change tlb_flush() argument to CPUState
Andreas Färber
2
-11
/
+30
2014-03-13
cputlb: Change tlb_flush_page() argument to CPUState
Andreas Färber
1
-4
/
+10
2014-03-13
exec: Change cpu_abort() argument to CPUState
Andreas Färber
2
-11
/
+26
2014-03-13
translate-all: Change cpu_restore_state() argument to CPUState
Andreas Färber
1
-1
/
+1
2014-03-13
cpu-exec: Change cpu_loop_exit() argument to CPUState
Andreas Färber
1
-4
/
+4
2014-03-13
exec: Change tlb_fill() argument to CPUState
Andreas Färber
1
-5
/
+7
2014-03-13
cpu: Move breakpoints field from CPU_COMMON to CPUState
Andreas Färber
3
-5
/
+5
2014-03-13
cpu: Move opaque field from CPU_COMMON to CPUState
Andreas Färber
1
-4
/
+5
2014-03-13
cpu: Move exception_index field from CPU_COMMON to CPUState
Andreas Färber
2
-20
/
+25
2014-03-13
cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook
Andreas Färber
4
-9
/
+16
2014-03-13
cpu: Factor out cpu_generic_init()
Andreas Färber
1
-13
/
+1
2014-03-13
cpu: Turn cpu_has_work() into a CPUClass hook
Andreas Färber
2
-6
/
+7
2014-03-13
target-arm: Clean up ENV_GET_CPU() usage
Andreas Färber
1
-5
/
+7
2014-03-10
target-arm: Implement WFE as a yield operation
Peter Maydell
4
-0
/
+18
2014-03-10
target-arm: Fix intptr_t vs tcg_target_long
Richard Henderson
1
-1
/
+1
2014-03-10
target-arm: Implements the ARM PMCCNTR register
Alistair Francis
2
-4
/
+89
2014-03-10
target-arm: Fix incorrect setting of E bit in CPSR
Peter Maydell
1
-1
/
+1
2014-02-26
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
Will Newton
5
-0
/
+100
2014-02-26
target-arm: Add utility function for checking AA32/64 state of an EL
Peter Maydell
1
-0
/
+16
2014-02-26
target-arm: Implement AArch64 view of CPACR
Peter Maydell
2
-2
/
+3
2014-02-26
target-arm: A64: Implement MSR (immediate) instructions
Peter Maydell
3
-1
/
+51
2014-02-26
target-arm: Store AIF bits in env->pstate for AArch32
Peter Maydell
3
-19
/
+30
2014-02-26
target-arm: A64: Implement WFI
Peter Maydell
1
-1
/
+4
2014-02-26
target-arm: Get MMU index information correct for A64 code
Peter Maydell
2
-4
/
+9
2014-02-26
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
Peter Maydell
1
-0
/
+4
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