| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2013-08-20 | target-arm: Support coprocessor registers which do I/O | Peter Maydell | 1 | -3/+13 |
| 2013-07-23 | cpu: Move singlestep_enabled field from CPU_COMMON to CPUState | Andreas Färber | 1 | -3/+4 |
| 2013-07-15 | target-arm: explicitly decode SEVL instruction | Mans Rullgard | 1 | -1/+2 |
| 2013-07-15 | target-arm: implement LDA/STL instructions | Mans Rullgard | 1 | -10/+119 |
| 2013-07-15 | target-arm: add feature flag for ARMv8 | Mans Rullgard | 1 | -0/+1 |
| 2013-07-09 | target-arm: Change gen_intermediate_code_internal() argument to ARMCPU | Andreas Färber | 1 | -4/+5 |
| 2013-06-28 | cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks | Andreas Färber | 1 | -2/+4 |
| 2013-06-14 | Merge remote-tracking branch 'pmaydell/target-arm.next' into staging | Anthony Liguori | 1 | -1/+1 |
| 2013-06-03 | Fix rfe instruction | Peter Chubb | 1 | -1/+1 |
| 2013-06-01 | Remove unnecessary break statements | Stefan Weil | 1 | -1/+0 |
| 2013-05-26 | target-arm: Remove gen_{ld,st}* definitions | Peter Maydell | 1 | -46/+0 |
| 2013-05-26 | target-arm: Remove gen_{ld,st}* from thumb2 decoder | Peter Maydell | 1 | -10/+20 |
| 2013-05-26 | target-arm: Remove gen_{ld,st}* from Thumb insns | Peter Maydell | 1 | -25/+46 |
| 2013-05-26 | target-arm: Remove gen_{ld,st}* from basic ARM insns | Peter Maydell | 1 | -32/+69 |
| 2013-05-26 | target-arm: Remove use of gen_{ld,st}* from ldrex/strex | Peter Maydell | 1 | -13/+18 |
| 2013-05-26 | target-arm: Remove uses of gen_{ld,st}* from Neon code | Peter Maydell | 1 | -18/+28 |
| 2013-05-26 | target-arm: Remove uses of gen_{ld,st}* from iWMMXt code | Peter Maydell | 1 | -8/+10 |
| 2013-05-26 | target-arm: Remove gen_ld64() and gen_st64() | Peter Maydell | 1 | -15/+4 |
| 2013-05-26 | target-arm: Don't use TCGv when we mean TCGv_i32 | Peter Maydell | 1 | -224/+229 |
| 2013-04-19 | target-arm: Reinsert missing return statement in ARM mode SRS decode | Peter Chubb | 1 | -0/+1 |
| 2013-03-05 | target-arm: Don't decode RFE or SRS on M profile cores | Peter Maydell | 1 | -2/+3 |
| 2013-03-05 | target-arm: Factor out handling of SRS instruction | Peter Maydell | 1 | -67/+69 |
| 2013-03-03 | gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end | Peter Maydell | 1 | -2/+2 |
| 2013-02-25 | target-arm: Fix sbc_CC carry | Richard Henderson | 1 | -24/+4 |
| 2013-02-25 | arm/translate.c: Fix adc_CC/sbc_CC implementation | Peter Crosthwaite | 1 | -2/+2 |
| 2013-02-23 | target-arm: Implement sbc_cc inline | Richard Henderson | 1 | -8/+39 |
| 2013-02-23 | target-arm: Implement adc_cc inline | Richard Henderson | 1 | -5/+34 |
| 2013-02-23 | target-arm: Use add2 in gen_add_CC | Richard Henderson | 1 | -4/+3 |
| 2013-02-23 | target-arm: Use mul[us]2 and add2 in umlal et al | Richard Henderson | 1 | -12/+14 |
| 2013-02-23 | target-arm: Use mul[us]2 in gen_mul[us]_i64_i32 | Richard Henderson | 1 | -16/+22 |
| 2013-01-30 | target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes | Peter Maydell | 1 | -1/+4 |
| 2012-12-19 | misc: move include files to include/qemu/ | Paolo Bonzini | 1 | -1/+1 |
| 2012-12-19 | exec: move include files to include/exec/ | Paolo Bonzini | 1 | -1/+1 |
| 2012-12-19 | build: kill libdis, move disassemblers to disas/ | Paolo Bonzini | 1 | -1/+1 |
| 2012-12-08 | TCG: Use gen_opc_instr_start from context instead of global variable. | Evgeny Voevodin | 1 | -3/+3 |
| 2012-12-08 | TCG: Use gen_opc_icount from context instead of global variable. | Evgeny Voevodin | 1 | -1/+1 |
| 2012-12-08 | TCG: Use gen_opc_pc from context instead of global variable. | Evgeny Voevodin | 1 | -2/+2 |
| 2012-11-17 | TCG: Use gen_opc_buf from context instead of global variable. | Evgeny Voevodin | 1 | -3/+3 |
| 2012-11-17 | TCG: Use gen_opc_ptr from context instead of global variable. | Evgeny Voevodin | 1 | -4/+4 |
| 2012-11-10 | disas: avoid using cpu_single_env | Blue Swirl | 1 | -1/+1 |
| 2012-10-24 | target-arm: Implement abs_i32 inline rather than as a helper | Peter Maydell | 1 | -2/+9 |
| 2012-10-24 | target-arm: Use TCG operation for Neon 64 bit negation | Peter Maydell | 1 | -1/+3 |
| 2012-10-17 | target-arm/translate: Fix RRX operands | Peter Crosthwaite | 1 | -1/+1 |
| 2012-10-05 | target-arm: use deposit instead of hardcoded version | Aurelien Jarno | 1 | -14/+6 |
| 2012-10-05 | target-arm: convert sar, shl and shr helpers to TCG | Aurelien Jarno | 1 | -6/+43 |
| 2012-10-05 | target-arm: convert add_cc and sub_cc helpers to TCG | Aurelien Jarno | 1 | -18/+48 |
| 2012-10-05 | target-arm: use globals for CC flags | Aurelien Jarno | 1 | -81/+46 |
| 2012-10-05 | target-arm: Reinstate display of VFP registers in cpu_dump_state | Peter Maydell | 1 | -26/+16 |
| 2012-09-27 | Emit debug_insn for CPU_LOG_TB_OP_OPT as well. | Richard Henderson | 1 | -1/+1 |
| 2012-09-15 | target-arm: final conversion to AREG0 free mode | Blue Swirl | 1 | -3/+3 |
