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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2014-06-24Fix new typos (found by codespell)Stefan Weil1-1/+1
2014-06-19target-arm: Add ULL suffix to calculation of page sizePeter Maydell1-1/+1
2014-06-19target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler1-18/+44
2014-06-09target-arm: Fix errors in writes to generic timer control registersPeter Maydell1-3/+3
2014-06-09target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell1-19/+6
2014-06-09target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell1-9/+8
2014-06-09target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler1-14/+14
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-2/+1
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-1/+1
2014-05-27target-arm: A64: Register VBAR_EL3Edgar E. Iglesias1-0/+5
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias1-0/+21
2014-05-27target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias1-1/+1
2014-05-27target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias1-0/+4
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias1-3/+3
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias1-5/+5
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias1-1/+2
2014-05-27target-arm: implement CPACR register logic for ARMv7Fabian Aggeler1-4/+28
2014-05-13target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell1-0/+7
2014-05-01target-arm: A64: Fix a typo when declaring TLBI opsEdgar E. Iglesias1-12/+12
2014-05-01target-arm: Make vbar_write 64bit friendly on 32bit hostsEdgar E. Iglesias1-1/+1
2014-05-01target-arm: Implement XScale cache lockdown operations as NOPsPeter Maydell1-0/+15
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell1-6/+33
2014-04-17target-arm: Implement RVBAR registerPeter Maydell1-0/+6
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell1-29/+24
2014-04-17target-arm: Implement auxiliary fault status registersPeter Maydell1-0/+9
2014-04-17target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell1-5/+91
2014-04-17target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell1-18/+43
2014-04-17target-arm: Implement ISR_EL1 registerPeter Maydell1-0/+18
2014-04-17target-arm: Implement AArch64 view of ACTLRPeter Maydell1-1/+2
2014-04-17target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell1-15/+18
2014-04-17target-arm: Implement AArch64 views of AArch32 ID registersPeter Maydell1-29/+44
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell1-0/+12
2014-04-17target-arm: Move arm_log_exception() into internals.hPeter Maydell1-31/+0
2014-04-17target-arm: Implement AArch64 SPSR_EL1Peter Maydell1-0/+4
2014-04-17target-arm: Implement SP_EL0, SP_EL1Peter Maydell1-0/+34
2014-04-17target-arm: Add AArch64 ELR_EL1 register.Peter Maydell1-0/+4
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring1-13/+25
2014-04-17target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell1-10/+14
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-5/+117
2014-04-17target-arm: Don't mention PMU in debug feature registerPeter Maydell1-1/+6
2014-04-17target-arm: Add v8 mmu translation supportRob Herring1-32/+77
2014-04-17target-arm: Provide syndrome information for MMU faultsRob Herring1-0/+12
2014-04-17target-arm: Define exception record for AArch64 exceptionsPeter Maydell1-9/+14
2014-04-17target-arm: Implement AArch64 DAIF system registerPeter Maydell1-0/+20
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell1-0/+1
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée1-27/+106
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée1-35/+163
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