summaryrefslogtreecommitdiff
path: root/target-arm/helper-a64.c
AgeCommit message (Expand)AuthorFilesLines
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows1-1/+1
2015-04-01target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)Peter Maydell1-1/+1
2015-02-13target-arm: Add 32/64-bit register syncGreg Bellows1-4/+1
2015-02-05target-arm: Squash input denormals in FRECPS and FRSQRTSPeter Maydell1-0/+12
2015-02-05Fix FMULX not squashing denormalized inputs when FZ is set.Xiangyu Hu1-0/+6
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows1-3/+3
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring1-0/+6
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring1-0/+3
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias1-0/+2
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+1
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias1-0/+1
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias1-0/+1
2014-09-29target-arm: A64: Correct updates to FAR and ESR on exceptionsEdgar E. Iglesias1-4/+3
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias1-11/+13
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias1-2/+2
2014-08-04target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias1-2/+2
2014-06-09target-arm: A64: Implement CRC instructionsPeter Maydell1-0/+30
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell1-30/+0
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-1/+1
2014-05-27target-arm: A64: Introduce aarch64_banked_spsr_index()Edgar E. Iglesias1-1/+1
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias1-1/+1
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias1-2/+2
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias1-2/+2
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring1-0/+76
2014-03-17target-arm: A64: Implement FCVTXNPeter Maydell1-0/+23
2014-03-17target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée1-0/+59
2014-03-17target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell1-0/+61
2014-03-17target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée1-0/+5
2014-03-17target-arm: A64: Implement PMULL instructionPeter Maydell1-0/+30
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell1-0/+60
2014-02-20target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée1-0/+19
2014-02-20target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell1-0/+26
2014-01-31target-arm: A64: Add SIMD TBL/TBLXMichael Matz1-0/+31
2014-01-08target-arm: A64: Add support for floating point compareClaudio Fontana1-0/+45
2013-12-17target-arm: A64: add support for 1-src CLS insnClaudio Fontana1-0/+10
2013-12-17target-arm: A64: add support for 1-src RBIT insnAlexander Graf1-0/+18
2013-12-17target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana1-0/+5
2013-12-17target-arm: A64: add support for 2-src data processing and DIVAlexander Graf1-0/+21
2013-12-17target-arm: A64: add stubs for a64 specific helpersAlexander Graf1-0/+25
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 05:32:16 +0000