index
:
sdk/emulator/qemu
1.0_post
2.0alpha
features/brillcodec_2i
features/camera
features/cnp
features/dr
features/qt_dr
features/smp
features/virtio-9p
features/vmodem
glesv3
master
opensrc_p2.3
opensrc_p2.3.1
opensrc_p2.3.2
opensrc_p2.4
opensrc_p3.0
opensrc_p4.0
sandbox/byungchul.so/tizen
sandbox/elebideau/tizen
sandbox/mmajewski2/maru-virgl-rendering-wip
sandbox/mmajewski2/standalone-virgl-wip
sandbox/pcoval/tizen
spin
tizen
tizen_2.0
tizen_2.1
tizen_2.2
tizen_3.0.m14.4_ivi
tizen_p2.3
tizen_p2.3.1
tizen_qemu_1.6
tizen_qemu_1.7
tizen_qemu_2.0
tizen_qemu_5.0.1
tizen_studio_1.2_p2.3
tizen_studio_1.2_p2.3.1
tizen_studio_1.2_p2.3.2
tizen_studio_1.2_p2.4
tizen_studio_1.2_p3.0
tizen_studio_1.3_p2.3
tizen_studio_1.3_p2.3.1
tizen_studio_1.3_p2.3.2
tizen_studio_1.3_p2.4
tizen_studio_1.3_p3.0
tizen_studio_2.0_p2.3
tizen_studio_2.0_p2.3.1
tizen_studio_2.0_p2.3.2
tizen_studio_2.0_p2.4
tizen_studio_2.0_p3.0
tizen_studio_2.0_p4.0
tizen_studio_2.0_p5.0
tizen_studio_3.0_p2.3
tizen_studio_3.0_p2.3.1
tizen_studio_3.0_p2.3.2
tizen_studio_3.0_p2.4
tizen_studio_3.0_p3.0
tizen_studio_3.0_p4.0
tizen_studio_3.0_p5.0
tizen_studio_3.5_p2.3
tizen_studio_3.5_p2.3.1
tizen_studio_3.5_p2.3.2
tizen_studio_3.5_p2.4
tizen_studio_3.5_p3.0
tizen_studio_3.5_p4.0
tizen_studio_3.5_p5.0
tizen_studio_3.5_p5.5
tizen_studio_4.0_p2.3
tizen_studio_4.0_p2.3.1
tizen_studio_4.0_p2.3.2
tizen_studio_4.0_p2.4
tizen_studio_4.0_p3.0
tizen_studio_4.0_p4.0
tizen_studio_4.0_p5.0
tizen_studio_4.0_p5.5
tizen_studio_4.0_p6.0
tizen_studio_4.5_p6.5
tizen_studio_5.0_p7.0
tizen_studio_5.5_p7.5
tizen_studio_5.5_p8.0
tizen_studio_6.0_p9.0
tizen_studio_p2.3
tizen_studio_p2.3.1
tizen_studio_p2.3.2
tizen_studio_p2.4
tizen_studio_p3.0
tizen_studio_p4.0
works/arg_renewal
Domain: SDK / Emulator;
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
/
cpu.c
Age
Commit message (
Expand
)
Author
Files
Lines
2016-06-17
target-arm: Add mp-affinity property for ARM CPU class
Pavel Fedin
1
-0
/
+1
2016-06-17
target-arm: Provide hook to tell GICv3 about changes of security state
Peter Maydell
1
-0
/
+9
2016-05-19
cpu: move exec-all.h inclusion out of cpu.h
Paolo Bonzini
1
-0
/
+1
2016-03-22
include/qemu/osdep.h: Don't include qapi/error.h
Markus Armbruster
1
-0
/
+1
2016-03-04
target-arm: cpu: Move cpu_is_big_endian to header
Peter Crosthwaite
1
-16
/
+3
2016-03-04
target-arm: implement SCTLR.B, drop bswap_code
Paolo Bonzini
1
-1
/
+1
2016-02-18
target-arm: Add the pmceid0 and pmceid1 registers
Alistair Francis
1
-0
/
+2
2016-02-11
target-arm: Implement checking of fired watchpoint
Sergey Fedorov
1
-0
/
+1
2016-02-03
target-arm: Don't report presence of EL2 if it doesn't exist
Peter Maydell
1
-0
/
+9
2016-01-27
gdb: provide the name of the architecture in the target.xml
David Hildenbrand
1
-0
/
+12
2016-01-21
target-arm: Implement cpu_get_phys_page_attrs_debug
Peter Maydell
1
-1
/
+1
2016-01-21
target-arm: Implement asidx_from_attrs
Peter Maydell
1
-0
/
+1
2016-01-21
target-arm: Add QOM property for Secure memory region
Peter Maydell
1
-0
/
+32
2016-01-18
target-arm: Clean up includes
Peter Maydell
1
-0
/
+1
2016-01-15
target-arm: support QMP dump-guest-memory
Andrew Jones
1
-0
/
+2
2016-01-13
error: Strip trailing '\n' from error string arguments (again)
Markus Armbruster
1
-1
/
+1
2015-12-17
target-arm: raise exception on misaligned LDREX operands
Andrew Baumann
1
-0
/
+1
2015-10-09
qdev: Protect device-list-properties against broken devices
Markus Armbruster
1
-0
/
+11
2015-09-07
target-arm: Refactor CPU affinity handling
Pavel Fedin
1
-1
/
+1
2015-09-07
arm: Remove hw_error() usages.
Peter Crosthwaite
1
-2
/
+2
2015-09-07
arm: cpu: assert() on no-EL2 virt IRQ error condition.
Peter Crosthwaite
1
-4
/
+1
2015-08-13
target-arm: Add the AArch64 view of the Secure physical timer
Peter Maydell
1
-0
/
+2
2015-08-13
target-arm: Add debug check for mismatched cpreg resets
Peter Maydell
1
-0
/
+23
2015-08-13
target-arm: Add the Hypervisor timer
Edgar E. Iglesias
1
-0
/
+2
2015-07-09
disas: arm: QOMify target specific disas setup
Peter Crosthwaite
1
-0
/
+35
2015-07-09
cpu: Change cpu_exec_init() arg to cpu, not env
Peter Crosthwaite
1
-1
/
+1
2015-07-09
cpu: Add Error argument to cpu_exec_init()
Bharata B Rao
1
-1
/
+1
2015-06-22
Include qapi/qmp/qerror.h exactly where needed
Markus Armbruster
1
-1
/
+0
2015-06-19
target-arm: Add support for Cortex-R5
Peter Crosthwaite
1
-0
/
+38
2015-06-19
target-arm: Add registers for PMSAv7
Peter Crosthwaite
1
-0
/
+6
2015-06-19
target-arm/helper.c: define MPUIR register
Peter Crosthwaite
1
-0
/
+18
2015-06-19
target-arm: Do not reset sysregs marked as ALIAS
Sergey Fedorov
1
-1
/
+1
2015-06-19
target-arm: Add the Cortex-M4 CPU
Aurelio C. Remonda
1
-0
/
+11
2015-06-15
arm: Add has-mpu property
Peter Crosthwaite
1
-0
/
+13
2015-06-15
target-arm: Add the THUMB_DSP feature
Aurelio C. Remonda
1
-0
/
+4
2015-06-15
target-arm: Use the kernel's idea of MPIDR if we're using KVM
Pavel Fedin
1
-0
/
+12
2015-05-29
target-arm: Update interrupt handling to use target EL
Greg Bellows
1
-20
/
+41
2015-05-29
target-arm: Move setting of exception info into tlb_fill
Peter Maydell
1
-0
/
+17
2015-04-26
target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
Sergey Fedorov
1
-1
/
+2
2015-04-26
target-arm: rename c1_coproc to cpacr_el1
Sergey Fedorov
1
-2
/
+2
2015-02-13
target-arm: Add CPU property to disable AArch64
Greg Bellows
1
-1
/
+4
2015-02-05
target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64
Pranavkumar Sawargaonkar
1
-0
/
+24
2015-02-05
target-arm: Change reset to highest available EL
Greg Bellows
1
-1
/
+8
2014-12-22
target-arm: add cpu feature EL3 to CPUs with Security Extensions
Fabian Aggeler
1
-0
/
+4
2014-12-22
target-arm: Add ARMCPU secure property
Greg Bellows
1
-0
/
+23
2014-12-22
target-arm: Add feature unset function
Greg Bellows
1
-0
/
+5
2014-12-11
target-arm: make IFAR/DFAR banked
Fabian Aggeler
1
-1
/
+1
2014-12-11
target-arm: add SCTLR_EL3 and make SCTLR banked
Fabian Aggeler
1
-2
/
+6
2014-11-04
target-arm: Separate out M profile cpu_exec_interrupt handling
Peter Maydell
1
-10
/
+39
2014-10-24
target-arm: Correct sense of the DCZID DZP bit
Peter Maydell
1
-2
/
+2
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