diff options
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/Makefile.objs | 2 | ||||
| -rw-r--r-- | target-mips/cpu.h | 16 | ||||
| -rw-r--r-- | target-mips/helper.h | 410 | ||||
| -rw-r--r-- | target-mips/op_helper.c | 1065 | ||||
| -rw-r--r-- | target-mips/translate.c | 754 |
5 files changed, 1162 insertions, 1085 deletions
diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs index 2e0e093e1f..ca20f21443 100644 --- a/target-mips/Makefile.objs +++ b/target-mips/Makefile.objs @@ -1,4 +1,2 @@ obj-y += translate.o op_helper.o helper.o cpu.o obj-$(CONFIG_SOFTMMU) += machine.o - -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 88d92f1182..b7a5112b7b 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -38,10 +38,10 @@ struct CPUMIPSTLBContext { uint32_t nb_tlb; uint32_t tlb_in_use; int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type); - void (*helper_tlbwi) (void); - void (*helper_tlbwr) (void); - void (*helper_tlbp) (void); - void (*helper_tlbr) (void); + void (*helper_tlbwi)(struct CPUMIPSState *env); + void (*helper_tlbwr)(struct CPUMIPSState *env); + void (*helper_tlbp)(struct CPUMIPSState *env); + void (*helper_tlbr)(struct CPUMIPSState *env); union { struct { r4k_tlb_t tlb[MIPS_TLB_MAX]; @@ -485,10 +485,10 @@ int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int target_ulong address, int rw, int access_type); int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type); -void r4k_helper_tlbwi (void); -void r4k_helper_tlbwr (void); -void r4k_helper_tlbp (void); -void r4k_helper_tlbr (void); +void r4k_helper_tlbwi(CPUMIPSState *env); +void r4k_helper_tlbwr(CPUMIPSState *env); +void r4k_helper_tlbp(CPUMIPSState *env); +void r4k_helper_tlbr(CPUMIPSState *env); void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr, int is_write, int is_exec, int unused, int size); diff --git a/target-mips/helper.h b/target-mips/helper.h index 76fb451e77..109ac37fd6 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -1,25 +1,25 @@ #include "def-helper.h" -DEF_HELPER_2(raise_exception_err, noreturn, i32, int) -DEF_HELPER_1(raise_exception, noreturn, i32) +DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) +DEF_HELPER_2(raise_exception, noreturn, env, i32) #ifdef TARGET_MIPS64 -DEF_HELPER_3(ldl, tl, tl, tl, int) -DEF_HELPER_3(ldr, tl, tl, tl, int) -DEF_HELPER_3(sdl, void, tl, tl, int) -DEF_HELPER_3(sdr, void, tl, tl, int) +DEF_HELPER_4(ldl, tl, env, tl, tl, int) +DEF_HELPER_4(ldr, tl, env, tl, tl, int) +DEF_HELPER_4(sdl, void, env, tl, tl, int) +DEF_HELPER_4(sdr, void, env, tl, tl, int) #endif -DEF_HELPER_3(lwl, tl, tl, tl, int) -DEF_HELPER_3(lwr, tl, tl, tl, int) -DEF_HELPER_3(swl, void, tl, tl, int) -DEF_HELPER_3(swr, void, tl, tl, int) +DEF_HELPER_4(lwl, tl, env, tl, tl, int) +DEF_HELPER_4(lwr, tl, env, tl, tl, int) +DEF_HELPER_4(swl, void, env, tl, tl, int) +DEF_HELPER_4(swr, void, env, tl, tl, int) #ifndef CONFIG_USER_ONLY -DEF_HELPER_2(ll, tl, tl, int) -DEF_HELPER_3(sc, tl, tl, tl, int) +DEF_HELPER_3(ll, tl, env, tl, int) +DEF_HELPER_4(sc, tl, env, tl, tl, int) #ifdef TARGET_MIPS64 -DEF_HELPER_2(lld, tl, tl, int) -DEF_HELPER_3(scd, tl, tl, tl, int) +DEF_HELPER_3(lld, tl, env, tl, int) +DEF_HELPER_4(scd, tl, env, tl, tl, int) #endif #endif @@ -28,195 +28,195 @@ DEF_HELPER_FLAGS_1(clz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) #ifdef TARGET_MIPS64 DEF_HELPER_FLAGS_1(dclo, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) DEF_HELPER_FLAGS_1(dclz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) -DEF_HELPER_2(dmult, void, tl, tl) -DEF_HELPER_2(dmultu, void, tl, tl) +DEF_HELPER_3(dmult, void, env, tl, tl) +DEF_HELPER_3(dmultu, void, env, tl, tl) #endif -DEF_HELPER_2(muls, tl, tl, tl) -DEF_HELPER_2(mulsu, tl, tl, tl) -DEF_HELPER_2(macc, tl, tl, tl) -DEF_HELPER_2(maccu, tl, tl, tl) -DEF_HELPER_2(msac, tl, tl, tl) -DEF_HELPER_2(msacu, tl, tl, tl) -DEF_HELPER_2(mulhi, tl, tl, tl) -DEF_HELPER_2(mulhiu, tl, tl, tl) -DEF_HELPER_2(mulshi, tl, tl, tl) -DEF_HELPER_2(mulshiu, tl, tl, tl) -DEF_HELPER_2(macchi, tl, tl, tl) -DEF_HELPER_2(macchiu, tl, tl, tl) -DEF_HELPER_2(msachi, tl, tl, tl) -DEF_HELPER_2(msachiu, tl, tl, tl) +DEF_HELPER_3(muls, tl, env, tl, tl) +DEF_HELPER_3(mulsu, tl, env, tl, tl) +DEF_HELPER_3(macc, tl, env, tl, tl) +DEF_HELPER_3(maccu, tl, env, tl, tl) +DEF_HELPER_3(msac, tl, env, tl, tl) +DEF_HELPER_3(msacu, tl, env, tl, tl) +DEF_HELPER_3(mulhi, tl, env, tl, tl) +DEF_HELPER_3(mulhiu, tl, env, tl, tl) +DEF_HELPER_3(mulshi, tl, env, tl, tl) +DEF_HELPER_3(mulshiu, tl, env, tl, tl) +DEF_HELPER_3(macchi, tl, env, tl, tl) +DEF_HELPER_3(macchiu, tl, env, tl, tl) +DEF_HELPER_3(msachi, tl, env, tl, tl) +DEF_HELPER_3(msachiu, tl, env, tl, tl) #ifndef CONFIG_USER_ONLY /* CP0 helpers */ -DEF_HELPER_0(mfc0_mvpcontrol, tl) -DEF_HELPER_0(mfc0_mvpconf0, tl) -DEF_HELPER_0(mfc0_mvpconf1, tl) -DEF_HELPER_0(mftc0_vpecontrol, tl) -DEF_HELPER_0(mftc0_vpeconf0, tl) -DEF_HELPER_0(mfc0_random, tl) -DEF_HELPER_0(mfc0_tcstatus, tl) -DEF_HELPER_0(mftc0_tcstatus, tl) -DEF_HELPER_0(mfc0_tcbind, tl) -DEF_HELPER_0(mftc0_tcbind, tl) -DEF_HELPER_0(mfc0_tcrestart, tl) -DEF_HELPER_0(mftc0_tcrestart, tl) -DEF_HELPER_0(mfc0_tchalt, tl) -DEF_HELPER_0(mftc0_tchalt, tl) -DEF_HELPER_0(mfc0_tccontext, tl) -DEF_HELPER_0(mftc0_tccontext, tl) -DEF_HELPER_0(mfc0_tcschedule, tl) -DEF_HELPER_0(mftc0_tcschedule, tl) -DEF_HELPER_0(mfc0_tcschefback, tl) -DEF_HELPER_0(mftc0_tcschefback, tl) -DEF_HELPER_0(mfc0_count, tl) -DEF_HELPER_0(mftc0_entryhi, tl) -DEF_HELPER_0(mftc0_status, tl) -DEF_HELPER_0(mftc0_cause, tl) -DEF_HELPER_0(mftc0_epc, tl) -DEF_HELPER_0(mftc0_ebase, tl) -DEF_HELPER_1(mftc0_configx, tl, tl) -DEF_HELPER_0(mfc0_lladdr, tl) -DEF_HELPER_1(mfc0_watchlo, tl, i32) -DEF_HELPER_1(mfc0_watchhi, tl, i32) -DEF_HELPER_0(mfc0_debug, tl) -DEF_HELPER_0(mftc0_debug, tl) +DEF_HELPER_1(mfc0_mvpcontrol, tl, env) +DEF_HELPER_1(mfc0_mvpconf0, tl, env) +DEF_HELPER_1(mfc0_mvpconf1, tl, env) +DEF_HELPER_1(mftc0_vpecontrol, tl, env) +DEF_HELPER_1(mftc0_vpeconf0, tl, env) +DEF_HELPER_1(mfc0_random, tl, env) +DEF_HELPER_1(mfc0_tcstatus, tl, env) +DEF_HELPER_1(mftc0_tcstatus, tl, env) +DEF_HELPER_1(mfc0_tcbind, tl, env) +DEF_HELPER_1(mftc0_tcbind, tl, env) +DEF_HELPER_1(mfc0_tcrestart, tl, env) +DEF_HELPER_1(mftc0_tcrestart, tl, env) +DEF_HELPER_1(mfc0_tchalt, tl, env) +DEF_HELPER_1(mftc0_tchalt, tl, env) +DEF_HELPER_1(mfc0_tccontext, tl, env) +DEF_HELPER_1(mftc0_tccontext, tl, env) +DEF_HELPER_1(mfc0_tcschedule, tl, env) +DEF_HELPER_1(mftc0_tcschedule, tl, env) +DEF_HELPER_1(mfc0_tcschefback, tl, env) +DEF_HELPER_1(mftc0_tcschefback, tl, env) +DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mftc0_entryhi, tl, env) +DEF_HELPER_1(mftc0_status, tl, env) +DEF_HELPER_1(mftc0_cause, tl, env) +DEF_HELPER_1(mftc0_epc, tl, env) +DEF_HELPER_1(mftc0_ebase, tl, env) +DEF_HELPER_2(mftc0_configx, tl, env, tl) +DEF_HELPER_1(mfc0_lladdr, tl, env) +DEF_HELPER_2(mfc0_watchlo, tl, env, i32) +DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_1(mfc0_debug, tl, env) +DEF_HELPER_1(mftc0_debug, tl, env) #ifdef TARGET_MIPS64 -DEF_HELPER_0(dmfc0_tcrestart, tl) -DEF_HELPER_0(dmfc0_tchalt, tl) -DEF_HELPER_0(dmfc0_tccontext, tl) -DEF_HELPER_0(dmfc0_tcschedule, tl) -DEF_HELPER_0(dmfc0_tcschefback, tl) -DEF_HELPER_0(dmfc0_lladdr, tl) -DEF_HELPER_1(dmfc0_watchlo, tl, i32) +DEF_HELPER_1(dmfc0_tcrestart, tl, env) +DEF_HELPER_1(dmfc0_tchalt, tl, env) +DEF_HELPER_1(dmfc0_tccontext, tl, env) +DEF_HELPER_1(dmfc0_tcschedule, tl, env) +DEF_HELPER_1(dmfc0_tcschefback, tl, env) +DEF_HELPER_1(dmfc0_lladdr, tl, env) +DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) #endif /* TARGET_MIPS64 */ -DEF_HELPER_1(mtc0_index, void, tl) -DEF_HELPER_1(mtc0_mvpcontrol, void, tl) -DEF_HELPER_1(mtc0_vpecontrol, void, tl) -DEF_HELPER_1(mttc0_vpecontrol, void, tl) -DEF_HELPER_1(mtc0_vpeconf0, void, tl) -DEF_HELPER_1(mttc0_vpeconf0, void, tl) -DEF_HELPER_1(mtc0_vpeconf1, void, tl) -DEF_HELPER_1(mtc0_yqmask, void, tl) -DEF_HELPER_1(mtc0_vpeopt, void, tl) -DEF_HELPER_1(mtc0_entrylo0, void, tl) -DEF_HELPER_1(mtc0_tcstatus, void, tl) -DEF_HELPER_1(mttc0_tcstatus, void, tl) -DEF_HELPER_1(mtc0_tcbind, void, tl) -DEF_HELPER_1(mttc0_tcbind, void, tl) -DEF_HELPER_1(mtc0_tcrestart, void, tl) -DEF_HELPER_1(mttc0_tcrestart, void, tl) -DEF_HELPER_1(mtc0_tchalt, void, tl) -DEF_HELPER_1(mttc0_tchalt, void, tl) -DEF_HELPER_1(mtc0_tccontext, void, tl) -DEF_HELPER_1(mttc0_tccontext, void, tl) -DEF_HELPER_1(mtc0_tcschedule, void, tl) -DEF_HELPER_1(mttc0_tcschedule, void, tl) -DEF_HELPER_1(mtc0_tcschefback, void, tl) -DEF_HELPER_1(mttc0_tcschefback, void, tl) -DEF_HELPER_1(mtc0_entrylo1, void, tl) -DEF_HELPER_1(mtc0_context, void, tl) -DEF_HELPER_1(mtc0_pagemask, void, tl) -DEF_HELPER_1(mtc0_pagegrain, void, tl) -DEF_HELPER_1(mtc0_wired, void, tl) -DEF_HELPER_1(mtc0_srsconf0, void, tl) -DEF_HELPER_1(mtc0_srsconf1, void, tl) -DEF_HELPER_1(mtc0_srsconf2, void, tl) -DEF_HELPER_1(mtc0_srsconf3, void, tl) -DEF_HELPER_1(mtc0_srsconf4, void, tl) -DEF_HELPER_1(mtc0_hwrena, void, tl) -DEF_HELPER_1(mtc0_count, void, tl) -DEF_HELPER_1(mtc0_entryhi, void, tl) -DEF_HELPER_1(mttc0_entryhi, void, tl) -DEF_HELPER_1(mtc0_compare, void, tl) -DEF_HELPER_1(mtc0_status, void, tl) -DEF_HELPER_1(mttc0_status, void, tl) -DEF_HELPER_1(mtc0_intctl, void, tl) -DEF_HELPER_1(mtc0_srsctl, void, tl) -DEF_HELPER_1(mtc0_cause, void, tl) -DEF_HELPER_1(mttc0_cause, void, tl) -DEF_HELPER_1(mtc0_ebase, void, tl) -DEF_HELPER_1(mttc0_ebase, void, tl) -DEF_HELPER_1(mtc0_config0, void, tl) -DEF_HELPER_1(mtc0_config2, void, tl) -DEF_HELPER_1(mtc0_lladdr, void, tl) -DEF_HELPER_2(mtc0_watchlo, void, tl, i32) -DEF_HELPER_2(mtc0_watchhi, void, tl, i32) -DEF_HELPER_1(mtc0_xcontext, void, tl) -DEF_HELPER_1(mtc0_framemask, void, tl) -DEF_HELPER_1(mtc0_debug, void, tl) -DEF_HELPER_1(mttc0_debug, void, tl) -DEF_HELPER_1(mtc0_performance0, void, tl) -DEF_HELPER_1(mtc0_taglo, void, tl) -DEF_HELPER_1(mtc0_datalo, void, tl) -DEF_HELPER_1(mtc0_taghi, void, tl) -DEF_HELPER_1(mtc0_datahi, void, tl) +DEF_HELPER_2(mtc0_index, void, env, tl) +DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) +DEF_HELPER_2(mtc0_yqmask, void, env, tl) +DEF_HELPER_2(mtc0_vpeopt, void, env, tl) +DEF_HELPER_2(mtc0_entrylo0, void, env, tl) +DEF_HELPER_2(mtc0_tcstatus, void, env, tl) +DEF_HELPER_2(mttc0_tcstatus, void, env, tl) +DEF_HELPER_2(mtc0_tcbind, void, env, tl) +DEF_HELPER_2(mttc0_tcbind, void, env, tl) +DEF_HELPER_2(mtc0_tcrestart, void, env, tl) +DEF_HELPER_2(mttc0_tcrestart, void, env, tl) +DEF_HELPER_2(mtc0_tchalt, void, env, tl) +DEF_HELPER_2(mttc0_tchalt, void, env, tl) +DEF_HELPER_2(mtc0_tccontext, void, env, tl) +DEF_HELPER_2(mttc0_tccontext, void, env, tl) +DEF_HELPER_2(mtc0_tcschedule, void, env, tl) +DEF_HELPER_2(mttc0_tcschedule, void, env, tl) +DEF_HELPER_2(mtc0_tcschefback, void, env, tl) +DEF_HELPER_2(mttc0_tcschefback, void, env, tl) +DEF_HELPER_2(mtc0_entrylo1, void, env, tl) +DEF_HELPER_2(mtc0_context, void, env, tl) +DEF_HELPER_2(mtc0_pagemask, void, env, tl) +DEF_HELPER_2(mtc0_pagegrain, void, env, tl) +DEF_HELPER_2(mtc0_wired, void, env, tl) +DEF_HELPER_2(mtc0_srsconf0, void, env, tl) +DEF_HELPER_2(mtc0_srsconf1, void, env, tl) +DEF_HELPER_2(mtc0_srsconf2, void, env, tl) +DEF_HELPER_2(mtc0_srsconf3, void, env, tl) +DEF_HELPER_2(mtc0_srsconf4, void, env, tl) +DEF_HELPER_2(mtc0_hwrena, void, env, tl) +DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_entryhi, void, env, tl) +DEF_HELPER_2(mttc0_entryhi, void, env, tl) +DEF_HELPER_2(mtc0_compare, void, env, tl) +DEF_HELPER_2(mtc0_status, void, env, tl) +DEF_HELPER_2(mttc0_status, void, env, tl) +DEF_HELPER_2(mtc0_intctl, void, env, tl) +DEF_HELPER_2(mtc0_srsctl, void, env, tl) +DEF_HELPER_2(mtc0_cause, void, env, tl) +DEF_HELPER_2(mttc0_cause, void, env, tl) +DEF_HELPER_2(mtc0_ebase, void, env, tl) +DEF_HELPER_2(mttc0_ebase, void, env, tl) +DEF_HELPER_2(mtc0_config0, void, env, tl) +DEF_HELPER_2(mtc0_config2, void, env, tl) +DEF_HELPER_2(mtc0_lladdr, void, env, tl) +DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) +DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_2(mtc0_xcontext, void, env, tl) +DEF_HELPER_2(mtc0_framemask, void, env, tl) +DEF_HELPER_2(mtc0_debug, void, env, tl) +DEF_HELPER_2(mttc0_debug, void, env, tl) +DEF_HELPER_2(mtc0_performance0, void, env, tl) +DEF_HELPER_2(mtc0_taglo, void, env, tl) +DEF_HELPER_2(mtc0_datalo, void, env, tl) +DEF_HELPER_2(mtc0_taghi, void, env, tl) +DEF_HELPER_2(mtc0_datahi, void, env, tl) /* MIPS MT functions */ -DEF_HELPER_1(mftgpr, tl, i32); -DEF_HELPER_1(mftlo, tl, i32) -DEF_HELPER_1(mfthi, tl, i32) -DEF_HELPER_1(mftacx, tl, i32) -DEF_HELPER_0(mftdsp, tl) -DEF_HELPER_2(mttgpr, void, tl, i32) -DEF_HELPER_2(mttlo, void, tl, i32) -DEF_HELPER_2(mtthi, void, tl, i32) -DEF_HELPER_2(mttacx, void, tl, i32) -DEF_HELPER_1(mttdsp, void, tl) +DEF_HELPER_2(mftgpr, tl, env, i32); +DEF_HELPER_2(mftlo, tl, env, i32) +DEF_HELPER_2(mfthi, tl, env, i32) +DEF_HELPER_2(mftacx, tl, env, i32) +DEF_HELPER_1(mftdsp, tl, env) +DEF_HELPER_3(mttgpr, void, env, tl, i32) +DEF_HELPER_3(mttlo, void, env, tl, i32) +DEF_HELPER_3(mtthi, void, env, tl, i32) +DEF_HELPER_3(mttacx, void, env, tl, i32) +DEF_HELPER_2(mttdsp, void, env, tl) DEF_HELPER_0(dmt, tl) DEF_HELPER_0(emt, tl) -DEF_HELPER_0(dvpe, tl) -DEF_HELPER_0(evpe, tl) +DEF_HELPER_1(dvpe, tl, env) +DEF_HELPER_1(evpe, tl, env) #endif /* !CONFIG_USER_ONLY */ /* microMIPS functions */ -DEF_HELPER_3(lwm, void, tl, tl, i32); -DEF_HELPER_3(swm, void, tl, tl, i32); +DEF_HELPER_4(lwm, void, env, tl, tl, i32); +DEF_HELPER_4(swm, void, env, tl, tl, i32); #ifdef TARGET_MIPS64 -DEF_HELPER_3(ldm, void, tl, tl, i32); -DEF_HELPER_3(sdm, void, tl, tl, i32); +DEF_HELPER_4(ldm, void, env, tl, tl, i32); +DEF_HELPER_4(sdm, void, env, tl, tl, i32); #endif DEF_HELPER_2(fork, void, tl, tl) -DEF_HELPER_1(yield, tl, tl) +DEF_HELPER_2(yield, tl, env, tl) /* CP1 functions */ -DEF_HELPER_1(cfc1, tl, i32) -DEF_HELPER_2(ctc1, void, tl, i32) +DEF_HELPER_2(cfc1, tl, env, i32) +DEF_HELPER_3(ctc1, void, env, tl, i32) -DEF_HELPER_1(float_cvtd_s, i64, i32) -DEF_HELPER_1(float_cvtd_w, i64, i32) -DEF_HELPER_1(float_cvtd_l, i64, i64) -DEF_HELPER_1(float_cvtl_d, i64, i64) -DEF_HELPER_1(float_cvtl_s, i64, i32) -DEF_HELPER_1(float_cvtps_pw, i64, i64) -DEF_HELPER_1(float_cvtpw_ps, i64, i64) -DEF_HELPER_1(float_cvts_d, i32, i64) -DEF_HELPER_1(float_cvts_w, i32, i32) -DEF_HELPER_1(float_cvts_l, i32, i64) -DEF_HELPER_1(float_cvts_pl, i32, i32) -DEF_HELPER_1(float_cvts_pu, i32, i32) -DEF_HELPER_1(float_cvtw_s, i32, i32) -DEF_HELPER_1(float_cvtw_d, i32, i64) +DEF_HELPER_2(float_cvtd_s, i64, env, i32) +DEF_HELPER_2(float_cvtd_w, i64, env, i32) +DEF_HELPER_2(float_cvtd_l, i64, env, i64) +DEF_HELPER_2(float_cvtl_d, i64, env, i64) +DEF_HELPER_2(float_cvtl_s, i64, env, i32) +DEF_HELPER_2(float_cvtps_pw, i64, env, i64) +DEF_HELPER_2(float_cvtpw_ps, i64, env, i64) +DEF_HELPER_2(float_cvts_d, i32, env, i64) +DEF_HELPER_2(float_cvts_w, i32, env, i32) +DEF_HELPER_2(float_cvts_l, i32, env, i64) +DEF_HELPER_2(float_cvts_pl, i32, env, i32) +DEF_HELPER_2(float_cvts_pu, i32, env, i32) +DEF_HELPER_2(float_cvtw_s, i32, env, i32) +DEF_HELPER_2(float_cvtw_d, i32, env, i64) -DEF_HELPER_2(float_addr_ps, i64, i64, i64) -DEF_HELPER_2(float_mulr_ps, i64, i64, i64) +DEF_HELPER_3(float_addr_ps, i64, env, i64, i64) +DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64) -#define FOP_PROTO(op) \ -DEF_HELPER_1(float_ ## op ## l_s, i64, i32) \ -DEF_HELPER_1(float_ ## op ## l_d, i64, i64) \ -DEF_HELPER_1(float_ ## op ## w_s, i32, i32) \ -DEF_HELPER_1(float_ ## op ## w_d, i32, i64) +#define FOP_PROTO(op) \ +DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \ +DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \ +DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \ +DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64) FOP_PROTO(round) FOP_PROTO(trunc) FOP_PROTO(ceil) FOP_PROTO(floor) #undef FOP_PROTO -#define FOP_PROTO(op) \ -DEF_HELPER_1(float_ ## op ## _s, i32, i32) \ -DEF_HELPER_1(float_ ## op ## _d, i64, i64) +#define FOP_PROTO(op) \ +DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \ +DEF_HELPER_2(float_ ## op ## _d, i64, env, i64) FOP_PROTO(sqrt) FOP_PROTO(rsqrt) FOP_PROTO(recip) @@ -228,14 +228,20 @@ DEF_HELPER_1(float_ ## op ## _d, i64, i64) \ DEF_HELPER_1(float_ ## op ## _ps, i64, i64) FOP_PROTO(abs) FOP_PROTO(chs) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \ +DEF_HELPER_2(float_ ## op ## _d, i64, env, i64) \ +DEF_HELPER_2(float_ ## op ## _ps, i64, env, i64) FOP_PROTO(recip1) FOP_PROTO(rsqrt1) #undef FOP_PROTO -#define FOP_PROTO(op) \ -DEF_HELPER_2(float_ ## op ## _s, i32, i32, i32) \ -DEF_HELPER_2(float_ ## op ## _d, i64, i64, i64) \ -DEF_HELPER_2(float_ ## op ## _ps, i64, i64, i64) +#define FOP_PROTO(op) \ +DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \ +DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64) \ +DEF_HELPER_3(float_ ## op ## _ps, i64, env, i64, i64) FOP_PROTO(add) FOP_PROTO(sub) FOP_PROTO(mul) @@ -244,23 +250,23 @@ FOP_PROTO(recip2) FOP_PROTO(rsqrt2) #undef FOP_PROTO -#define FOP_PROTO(op) \ -DEF_HELPER_3(float_ ## op ## _s, i32, i32, i32, i32) \ -DEF_HELPER_3(float_ ## op ## _d, i64, i64, i64, i64) \ -DEF_HELPER_3(float_ ## op ## _ps, i64, i64, i64, i64) +#define FOP_PROTO(op) \ +DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \ +DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64) \ +DEF_HELPER_4(float_ ## op ## _ps, i64, env, i64, i64, i64) FOP_PROTO(muladd) FOP_PROTO(mulsub) FOP_PROTO(nmuladd) FOP_PROTO(nmulsub) #undef FOP_PROTO -#define FOP_PROTO(op) \ -DEF_HELPER_3(cmp_d_ ## op, void, i64, i64, int) \ -DEF_HELPER_3(cmpabs_d_ ## op, void, i64, i64, int) \ -DEF_HELPER_3(cmp_s_ ## op, void, i32, i32, int) \ -DEF_HELPER_3(cmpabs_s_ ## op, void, i32, i32, int) \ -DEF_HELPER_3(cmp_ps_ ## op, void, i64, i64, int) \ -DEF_HELPER_3(cmpabs_ps_ ## op, void, i64, i64, int) +#define FOP_PROTO(op) \ +DEF_HELPER_4(cmp_d_ ## op, void, env, i64, i64, int) \ +DEF_HELPER_4(cmpabs_d_ ## op, void, env, i64, i64, int) \ +DEF_HELPER_4(cmp_s_ ## op, void, env, i32, i32, int) \ +DEF_HELPER_4(cmpabs_s_ ## op, void, env, i32, i32, int) \ +DEF_HELPER_4(cmp_ps_ ## op, void, env, i64, i64, int) \ +DEF_HELPER_4(cmpabs_ps_ ## op, void, env, i64, i64, int) FOP_PROTO(f) FOP_PROTO(un) FOP_PROTO(eq) @@ -281,20 +287,20 @@ FOP_PROTO(ngt) /* Special functions */ #ifndef CONFIG_USER_ONLY -DEF_HELPER_0(tlbwi, void) -DEF_HELPER_0(tlbwr, void) -DEF_HELPER_0(tlbp, void) -DEF_HELPER_0(tlbr, void) -DEF_HELPER_0(di, tl) -DEF_HELPER_0(ei, tl) -DEF_HELPER_0(eret, void) -DEF_HELPER_0(deret, void) +DEF_HELPER_1(tlbwi, void, env) +DEF_HELPER_1(tlbwr, void, env) +DEF_HELPER_1(tlbp, void, env) +DEF_HELPER_1(tlbr, void, env) +DEF_HELPER_1(di, tl, env) +DEF_HELPER_1(ei, tl, env) +DEF_HELPER_1(eret, void, env) +DEF_HELPER_1(deret, void, env) #endif /* !CONFIG_USER_ONLY */ -DEF_HELPER_0(rdhwr_cpunum, tl) -DEF_HELPER_0(rdhwr_synci_step, tl) -DEF_HELPER_0(rdhwr_cc, tl) -DEF_HELPER_0(rdhwr_ccres, tl) -DEF_HELPER_1(pmon, void, int) -DEF_HELPER_0(wait, void) +DEF_HELPER_1(rdhwr_cpunum, tl, env) +DEF_HELPER_1(rdhwr_synci_step, tl, env) +DEF_HELPER_1(rdhwr_cc, tl, env) +DEF_HELPER_1(rdhwr_ccres, tl, env) +DEF_HELPER_2(pmon, void, env, int) +DEF_HELPER_1(wait, void, env) #include "def-helper.h" diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 3d242aafda..ce5ddaf050 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -18,8 +18,6 @@ */ #include <stdlib.h> #include "cpu.h" -#include "dyngen-exec.h" - #include "host-utils.h" #include "helper.h" @@ -35,7 +33,8 @@ static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); /*****************************************************************************/ /* Exceptions processing helpers */ -void helper_raise_exception_err (uint32_t exception, int error_code) +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) { #if 1 if (exception < 0x100) @@ -46,13 +45,13 @@ void helper_raise_exception_err (uint32_t exception, int error_code) cpu_loop_exit(env); } -void helper_raise_exception (uint32_t exception) +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) { - helper_raise_exception_err(exception, 0); + helper_raise_exception_err(env, exception, 0); } #if !defined(CONFIG_USER_ONLY) -static void do_restore_state(uintptr_t pc) +static void do_restore_state(CPUMIPSState *env, uintptr_t pc) { TranslationBlock *tb; @@ -65,20 +64,22 @@ static void do_restore_state(uintptr_t pc) #if defined(CONFIG_USER_ONLY) #define HELPER_LD(name, insn, type) \ -static inline type do_##name(target_ulong addr, int mem_idx) \ +static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ + int mem_idx) \ { \ return (type) insn##_raw(addr); \ } #else #define HELPER_LD(name, insn, type) \ -static inline type do_##name(target_ulong addr, int mem_idx) \ +static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ + int mem_idx) \ { \ switch (mem_idx) \ { \ - case 0: return (type) insn##_kernel(addr); break; \ - case 1: return (type) insn##_super(addr); break; \ + case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ + case 1: return (type) cpu_##insn##_super(env, addr); break; \ default: \ - case 2: return (type) insn##_user(addr); break; \ + case 2: return (type) cpu_##insn##_user(env, addr); break; \ } \ } #endif @@ -91,20 +92,22 @@ HELPER_LD(ld, ldq, int64_t) #if defined(CONFIG_USER_ONLY) #define HELPER_ST(name, insn, type) \ -static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ + type val, int mem_idx) \ { \ insn##_raw(addr, val); \ } #else #define HELPER_ST(name, insn, type) \ -static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ + type val, int mem_idx) \ { \ switch (mem_idx) \ { \ - case 0: insn##_kernel(addr, val); break; \ - case 1: insn##_super(addr, val); break; \ + case 0: cpu_##insn##_kernel(env, addr, val); break; \ + case 1: cpu_##insn##_super(env, addr, val); break; \ default: \ - case 2: insn##_user(addr, val); break; \ + case 2: cpu_##insn##_user(env, addr, val); break; \ } \ } #endif @@ -138,12 +141,12 @@ target_ulong helper_dclz (target_ulong arg1) #endif /* TARGET_MIPS64 */ /* 64 bits arithmetic for 32 bits hosts */ -static inline uint64_t get_HILO (void) +static inline uint64_t get_HILO(CPUMIPSState *env) { return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; } -static inline target_ulong set_HIT0_LO(uint64_t HILO) +static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) { target_ulong tmp; env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); @@ -151,7 +154,7 @@ static inline target_ulong set_HIT0_LO(uint64_t HILO) return tmp; } -static inline target_ulong set_HI_LOT0(uint64_t HILO) +static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) { target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); env->active_tc.HI[0] = (int32_t)(HILO >> 32); @@ -159,91 +162,110 @@ static inline target_ulong set_HI_LOT0(uint64_t HILO) } /* Multiplication variants of the vr54xx. */ -target_ulong helper_muls (target_ulong arg1, target_ulong arg2) +target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0(0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2)); } -target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0(0 - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); } -target_ulong helper_macc (target_ulong arg1, target_ulong arg2) +target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((int64_t)get_HILO() + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_macchi (target_ulong arg1, target_ulong arg2) +target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((int64_t)get_HILO() + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_maccu (target_ulong arg1, target_ulong arg2) +target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HI_LOT0(env, (uint64_t)get_HILO(env) + + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, (uint64_t)get_HILO(env) + + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_msac (target_ulong arg1, target_ulong arg2) +target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((int64_t)get_HILO() - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_msachi (target_ulong arg1, target_ulong arg2) +target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((int64_t)get_HILO() - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_msacu (target_ulong arg1, target_ulong arg2) +target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HI_LOT0(env, (uint64_t)get_HILO(env) - + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, (uint64_t)get_HILO(env) - + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); } -target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); } -target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO(0 - (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO(0 - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); } #ifdef TARGET_MIPS64 -void helper_dmult (target_ulong arg1, target_ulong arg2) +void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) { muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); } -void helper_dmultu (target_ulong arg1, target_ulong arg2) +void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) { mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); } @@ -251,7 +273,9 @@ void helper_dmultu (target_ulong arg1, target_ulong arg2) #ifndef CONFIG_USER_ONLY -static inline target_phys_addr_t do_translate_address(target_ulong address, int rw) +static inline target_phys_addr_t do_translate_address(CPUMIPSState *env, + target_ulong address, + int rw) { target_phys_addr_t lladdr; @@ -265,10 +289,10 @@ static inline target_phys_addr_t do_translate_address(target_ulong address, int } #define HELPER_LD_ATOMIC(name, insn) \ -target_ulong helper_##name(target_ulong arg, int mem_idx) \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ { \ - env->lladdr = do_translate_address(arg, 0); \ - env->llval = do_##insn(arg, mem_idx); \ + env->lladdr = do_translate_address(env, arg, 0); \ + env->llval = do_##insn(env, arg, mem_idx); \ return env->llval; \ } HELPER_LD_ATOMIC(ll, lw) @@ -278,18 +302,19 @@ HELPER_LD_ATOMIC(lld, ld) #undef HELPER_LD_ATOMIC #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ -target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ + target_ulong arg2, int mem_idx) \ { \ target_long tmp; \ \ if (arg2 & almask) { \ env->CP0_BadVAddr = arg2; \ - helper_raise_exception(EXCP_AdES); \ + helper_raise_exception(env, EXCP_AdES); \ } \ - if (do_translate_address(arg2, 1) == env->lladdr) { \ - tmp = do_##ld_insn(arg2, mem_idx); \ + if (do_translate_address(env, arg2, 1) == env->lladdr) { \ + tmp = do_##ld_insn(env, arg2, mem_idx); \ if (tmp == env->llval) { \ - do_##st_insn(arg2, arg1, mem_idx); \ + do_##st_insn(env, arg2, arg1, mem_idx); \ return 1; \ } \ } \ @@ -310,80 +335,84 @@ HELPER_ST_ATOMIC(scd, ld, sd, 0x7) #define GET_OFFSET(addr, offset) (addr - (offset)) #endif -target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { target_ulong tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); if (GET_LMASK(arg2) <= 2) { - tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx); arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); } if (GET_LMASK(arg2) <= 1) { - tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx); arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); } if (GET_LMASK(arg2) == 0) { - tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx); arg1 = (arg1 & 0xFFFFFF00) | tmp; } return (int32_t)arg1; } -target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { target_ulong tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0xFFFFFF00) | tmp; if (GET_LMASK(arg2) >= 1) { - tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx); arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); } if (GET_LMASK(arg2) >= 2) { - tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx); arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); } if (GET_LMASK(arg2) == 3) { - tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx); arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); } return (int32_t)arg1; } -void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx); if (GET_LMASK(arg2) <= 2) - do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK(arg2) <= 1) - do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK(arg2) == 0) - do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); + do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); } -void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)arg1, mem_idx); + do_sb(env, arg2, (uint8_t)arg1, mem_idx); if (GET_LMASK(arg2) >= 1) - do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK(arg2) >= 2) - do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK(arg2) == 3) - do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); } #if defined(TARGET_MIPS64) @@ -396,167 +425,172 @@ void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) #define GET_LMASK64(v) (((v) & 7) ^ 7) #endif -target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { uint64_t tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); if (GET_LMASK64(arg2) <= 6) { - tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx); arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); } if (GET_LMASK64(arg2) <= 5) { - tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx); arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); } if (GET_LMASK64(arg2) <= 4) { - tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx); arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); } if (GET_LMASK64(arg2) <= 3) { - tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 4), mem_idx); arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); } if (GET_LMASK64(arg2) <= 2) { - tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); } if (GET_LMASK64(arg2) <= 1) { - tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); } if (GET_LMASK64(arg2) == 0) { - tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; } return arg1; } -target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { uint64_t tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; if (GET_LMASK64(arg2) >= 1) { - tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); } if (GET_LMASK64(arg2) >= 2) { - tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); } if (GET_LMASK64(arg2) >= 3) { - tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx); arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); } if (GET_LMASK64(arg2) >= 4) { - tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx); arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); } if (GET_LMASK64(arg2) >= 5) { - tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx); arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); } if (GET_LMASK64(arg2) >= 6) { - tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx); arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); } if (GET_LMASK64(arg2) == 7) { - tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx); arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); } return arg1; } -void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx); + do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx); if (GET_LMASK64(arg2) <= 6) - do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); + do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); if (GET_LMASK64(arg2) <= 5) - do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); + do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); if (GET_LMASK64(arg2) <= 4) - do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); + do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); if (GET_LMASK64(arg2) <= 3) - do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); if (GET_LMASK64(arg2) <= 2) - do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK64(arg2) <= 1) - do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK64(arg2) <= 0) - do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); + do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); } -void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)arg1, mem_idx); + do_sb(env, arg2, (uint8_t)arg1, mem_idx); if (GET_LMASK64(arg2) >= 1) - do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK64(arg2) >= 2) - do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK64(arg2) >= 3) - do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); if (GET_LMASK64(arg2) >= 4) - do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); + do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); if (GET_LMASK64(arg2) >= 5) - do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); + do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); if (GET_LMASK64(arg2) >= 6) - do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); + do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); if (GET_LMASK64(arg2) == 7) - do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); + do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); } #endif /* TARGET_MIPS64 */ static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; -void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef ldfun -#define ldfun ldl_raw +#define ldfun(env, addr) ldl_raw(addr) #else - uint32_t (*ldfun)(target_ulong); + uint32_t (*ldfun)(CPUMIPSState *env, target_ulong); switch (mem_idx) { - case 0: ldfun = ldl_kernel; break; - case 1: ldfun = ldl_super; break; + case 0: ldfun = cpu_ldl_kernel; break; + case 1: ldfun = cpu_ldl_super; break; default: - case 2: ldfun = ldl_user; break; + case 2: ldfun = cpu_ldl_user; break; } #endif @@ -564,32 +598,33 @@ void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr); + env->active_tc.gpr[multiple_regs[i]] = (target_long)ldfun(env, addr); addr += 4; } } if (do_r31) { - env->active_tc.gpr[31] = (target_long) ldfun(addr); + env->active_tc.gpr[31] = (target_long)ldfun(env, addr); } } -void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef stfun -#define stfun stl_raw +#define stfun(env, addr, val) stl_raw(addr, val) #else - void (*stfun)(target_ulong, uint32_t); + void (*stfun)(CPUMIPSState *env, target_ulong, uint32_t); switch (mem_idx) { - case 0: stfun = stl_kernel; break; - case 1: stfun = stl_super; break; + case 0: stfun = cpu_stl_kernel; break; + case 1: stfun = cpu_stl_super; break; default: - case 2: stfun = stl_user; break; + case 2: stfun = cpu_stl_user; break; } #endif @@ -597,33 +632,34 @@ void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - stfun(addr, env->active_tc.gpr[multiple_regs[i]]); + stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); addr += 4; } } if (do_r31) { - stfun(addr, env->active_tc.gpr[31]); + stfun(env, addr, env->active_tc.gpr[31]); } } #if defined(TARGET_MIPS64) -void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef ldfun -#define ldfun ldq_raw +#define ldfun(env, addr) ldq_raw(addr) #else - uint64_t (*ldfun)(target_ulong); + uint64_t (*ldfun)(CPUMIPSState *env, target_ulong); switch (mem_idx) { - case 0: ldfun = ldq_kernel; break; - case 1: ldfun = ldq_super; break; + case 0: ldfun = cpu_ldq_kernel; break; + case 1: ldfun = cpu_ldq_super; break; default: - case 2: ldfun = ldq_user; break; + case 2: ldfun = cpu_ldq_user; break; } #endif @@ -631,32 +667,33 @@ void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = ldfun(addr); + env->active_tc.gpr[multiple_regs[i]] = ldfun(env, addr); addr += 8; } } if (do_r31) { - env->active_tc.gpr[31] = ldfun(addr); + env->active_tc.gpr[31] = ldfun(env, addr); } } -void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef stfun -#define stfun stq_raw +#define stfun(env, addr, val) stq_raw(addr, val) #else - void (*stfun)(target_ulong, uint64_t); + void (*stfun)(CPUMIPSState *env, target_ulong, uint64_t); switch (mem_idx) { - case 0: stfun = stq_kernel; break; - case 1: stfun = stq_super; break; + case 0: stfun = cpu_stq_kernel; break; + case 1: stfun = cpu_stq_super; break; default: - case 2: stfun = stq_user; break; + case 2: stfun = cpu_stq_user; break; } #endif @@ -664,13 +701,13 @@ void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - stfun(addr, env->active_tc.gpr[multiple_regs[i]]); + stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); addr += 8; } } if (do_r31) { - stfun(addr, env->active_tc.gpr[31]); + stfun(env, addr, env->active_tc.gpr[31]); } } #endif @@ -723,7 +760,7 @@ static inline void mips_tc_sleep(CPUMIPSState *c, int tc) FIXME: This code assumes that all VPEs have the same number of TCs, which depends on runtime setup. Can probably be fixed by walking the list of CPUMIPSStates. */ -static CPUMIPSState *mips_cpu_map_tc(int *tc) +static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) { CPUMIPSState *other; int vpe_idx, nr_threads = env->nr_threads; @@ -750,7 +787,7 @@ static CPUMIPSState *mips_cpu_map_tc(int *tc) These helper call synchronizes the regs for a given cpu. */ /* Called for updates to CP0_Status. */ -static void sync_c0_status(CPUMIPSState *cpu, int tc) +static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) { int32_t tcstatus, *tcst; uint32_t v = cpu->CP0_Status; @@ -785,7 +822,8 @@ static void sync_c0_status(CPUMIPSState *cpu, int tc) } /* Called for updates to CP0_TCStatus. */ -static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, target_ulong v) +static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, + target_ulong v) { uint32_t status; uint32_t tcu, tmx, tasid, tksu; @@ -834,35 +872,35 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) } /* CP0 helpers */ -target_ulong helper_mfc0_mvpcontrol (void) +target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) { return env->mvp->CP0_MVPControl; } -target_ulong helper_mfc0_mvpconf0 (void) +target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) { return env->mvp->CP0_MVPConf0; } -target_ulong helper_mfc0_mvpconf1 (void) +target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) { return env->mvp->CP0_MVPConf1; } -target_ulong helper_mfc0_random (void) +target_ulong helper_mfc0_random(CPUMIPSState *env) { return (int32_t)cpu_mips_get_random(env); } -target_ulong helper_mfc0_tcstatus (void) +target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) { return env->active_tc.CP0_TCStatus; } -target_ulong helper_mftc0_tcstatus(void) +target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCStatus; @@ -870,15 +908,15 @@ target_ulong helper_mftc0_tcstatus(void) return other->tcs[other_tc].CP0_TCStatus; } -target_ulong helper_mfc0_tcbind (void) +target_ulong helper_mfc0_tcbind(CPUMIPSState *env) { return env->active_tc.CP0_TCBind; } -target_ulong helper_mftc0_tcbind(void) +target_ulong helper_mftc0_tcbind(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCBind; @@ -886,15 +924,15 @@ target_ulong helper_mftc0_tcbind(void) return other->tcs[other_tc].CP0_TCBind; } -target_ulong helper_mfc0_tcrestart (void) +target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) { return env->active_tc.PC; } -target_ulong helper_mftc0_tcrestart(void) +target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.PC; @@ -902,15 +940,15 @@ target_ulong helper_mftc0_tcrestart(void) return other->tcs[other_tc].PC; } -target_ulong helper_mfc0_tchalt (void) +target_ulong helper_mfc0_tchalt(CPUMIPSState *env) { return env->active_tc.CP0_TCHalt; } -target_ulong helper_mftc0_tchalt(void) +target_ulong helper_mftc0_tchalt(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCHalt; @@ -918,15 +956,15 @@ target_ulong helper_mftc0_tchalt(void) return other->tcs[other_tc].CP0_TCHalt; } -target_ulong helper_mfc0_tccontext (void) +target_ulong helper_mfc0_tccontext(CPUMIPSState *env) { return env->active_tc.CP0_TCContext; } -target_ulong helper_mftc0_tccontext(void) +target_ulong helper_mftc0_tccontext(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCContext; @@ -934,15 +972,15 @@ target_ulong helper_mftc0_tccontext(void) return other->tcs[other_tc].CP0_TCContext; } -target_ulong helper_mfc0_tcschedule (void) +target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) { return env->active_tc.CP0_TCSchedule; } -target_ulong helper_mftc0_tcschedule(void) +target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCSchedule; @@ -950,15 +988,15 @@ target_ulong helper_mftc0_tcschedule(void) return other->tcs[other_tc].CP0_TCSchedule; } -target_ulong helper_mfc0_tcschefback (void) +target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) { return env->active_tc.CP0_TCScheFBack; } -target_ulong helper_mftc0_tcschefback(void) +target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCScheFBack; @@ -966,24 +1004,24 @@ target_ulong helper_mftc0_tcschefback(void) return other->tcs[other_tc].CP0_TCScheFBack; } -target_ulong helper_mfc0_count (void) +target_ulong helper_mfc0_count(CPUMIPSState *env) { return (int32_t)cpu_mips_get_count(env); } -target_ulong helper_mftc0_entryhi(void) +target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_EntryHi; } -target_ulong helper_mftc0_cause(void) +target_ulong helper_mftc0_cause(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int32_t tccause; - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) { tccause = other->CP0_Cause; @@ -994,30 +1032,30 @@ target_ulong helper_mftc0_cause(void) return tccause; } -target_ulong helper_mftc0_status(void) +target_ulong helper_mftc0_status(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_Status; } -target_ulong helper_mfc0_lladdr (void) +target_ulong helper_mfc0_lladdr(CPUMIPSState *env) { return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); } -target_ulong helper_mfc0_watchlo (uint32_t sel) +target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) { return (int32_t)env->CP0_WatchLo[sel]; } -target_ulong helper_mfc0_watchhi (uint32_t sel) +target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) { return env->CP0_WatchHi[sel]; } -target_ulong helper_mfc0_debug (void) +target_ulong helper_mfc0_debug(CPUMIPSState *env) { target_ulong t0 = env->CP0_Debug; if (env->hflags & MIPS_HFLAG_DM) @@ -1026,11 +1064,11 @@ target_ulong helper_mfc0_debug (void) return t0; } -target_ulong helper_mftc0_debug(void) +target_ulong helper_mftc0_debug(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int32_t tcstatus; - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) tcstatus = other->active_tc.CP0_Debug_tcstatus; @@ -1043,43 +1081,43 @@ target_ulong helper_mftc0_debug(void) } #if defined(TARGET_MIPS64) -target_ulong helper_dmfc0_tcrestart (void) +target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) { return env->active_tc.PC; } -target_ulong helper_dmfc0_tchalt (void) +target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) { return env->active_tc.CP0_TCHalt; } -target_ulong helper_dmfc0_tccontext (void) +target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) { return env->active_tc.CP0_TCContext; } -target_ulong helper_dmfc0_tcschedule (void) +target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) { return env->active_tc.CP0_TCSchedule; } -target_ulong helper_dmfc0_tcschefback (void) +target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) { return env->active_tc.CP0_TCScheFBack; } -target_ulong helper_dmfc0_lladdr (void) +target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) { return env->lladdr >> env->CP0_LLAddr_shift; } -target_ulong helper_dmfc0_watchlo (uint32_t sel) +target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) { return env->CP0_WatchLo[sel]; } #endif /* TARGET_MIPS64 */ -void helper_mtc0_index (target_ulong arg1) +void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) { int num = 1; unsigned int tmp = env->tlb->nb_tlb; @@ -1091,7 +1129,7 @@ void helper_mtc0_index (target_ulong arg1) env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); } -void helper_mtc0_mvpcontrol (target_ulong arg1) +void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = 0; uint32_t newval; @@ -1108,7 +1146,7 @@ void helper_mtc0_mvpcontrol (target_ulong arg1) env->mvp->CP0_MVPControl = newval; } -void helper_mtc0_vpecontrol (target_ulong arg1) +void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) { uint32_t mask; uint32_t newval; @@ -1125,10 +1163,10 @@ void helper_mtc0_vpecontrol (target_ulong arg1) env->CP0_VPEControl = newval; } -void helper_mttc0_vpecontrol(target_ulong arg1) +void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); uint32_t mask; uint32_t newval; @@ -1141,23 +1179,23 @@ void helper_mttc0_vpecontrol(target_ulong arg1) other->CP0_VPEControl = newval; } -target_ulong helper_mftc0_vpecontrol(void) +target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); /* FIXME: Mask away return zero on read bits. */ return other->CP0_VPEControl; } -target_ulong helper_mftc0_vpeconf0(void) +target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_VPEConf0; } -void helper_mtc0_vpeconf0 (target_ulong arg1) +void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = 0; uint32_t newval; @@ -1174,10 +1212,10 @@ void helper_mtc0_vpeconf0 (target_ulong arg1) env->CP0_VPEConf0 = newval; } -void helper_mttc0_vpeconf0(target_ulong arg1) +void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); uint32_t mask = 0; uint32_t newval; @@ -1188,7 +1226,7 @@ void helper_mttc0_vpeconf0(target_ulong arg1) other->CP0_VPEConf0 = newval; } -void helper_mtc0_vpeconf1 (target_ulong arg1) +void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = 0; uint32_t newval; @@ -1206,25 +1244,25 @@ void helper_mtc0_vpeconf1 (target_ulong arg1) env->CP0_VPEConf1 = newval; } -void helper_mtc0_yqmask (target_ulong arg1) +void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) { /* Yield qualifier inputs not implemented. */ env->CP0_YQMask = 0x00000000; } -void helper_mtc0_vpeopt (target_ulong arg1) +void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) { env->CP0_VPEOpt = arg1 & 0x0000ffff; } -void helper_mtc0_entrylo0 (target_ulong arg1) +void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) { /* Large physaddr (PABITS) not implemented */ /* 1k pages not implemented */ env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; } -void helper_mtc0_tcstatus (target_ulong arg1) +void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = env->CP0_TCStatus_rw_bitmask; uint32_t newval; @@ -1235,10 +1273,10 @@ void helper_mtc0_tcstatus (target_ulong arg1) sync_c0_tcstatus(env, env->current_tc, newval); } -void helper_mttc0_tcstatus (target_ulong arg1) +void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCStatus = arg1; @@ -1247,7 +1285,7 @@ void helper_mttc0_tcstatus (target_ulong arg1) sync_c0_tcstatus(other, other_tc, arg1); } -void helper_mtc0_tcbind (target_ulong arg1) +void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = (1 << CP0TCBd_TBE); uint32_t newval; @@ -1258,12 +1296,12 @@ void helper_mtc0_tcbind (target_ulong arg1) env->active_tc.CP0_TCBind = newval; } -void helper_mttc0_tcbind (target_ulong arg1) +void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); uint32_t mask = (1 << CP0TCBd_TBE); uint32_t newval; - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) mask |= (1 << CP0TCBd_CurVPE); @@ -1276,7 +1314,7 @@ void helper_mttc0_tcbind (target_ulong arg1) } } -void helper_mtc0_tcrestart (target_ulong arg1) +void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) { env->active_tc.PC = arg1; env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); @@ -1284,10 +1322,10 @@ void helper_mtc0_tcrestart (target_ulong arg1) /* MIPS16 not implemented. */ } -void helper_mttc0_tcrestart (target_ulong arg1) +void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) { other->active_tc.PC = arg1; @@ -1302,7 +1340,7 @@ void helper_mttc0_tcrestart (target_ulong arg1) } } -void helper_mtc0_tchalt (target_ulong arg1) +void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCHalt = arg1 & 0x1; @@ -1314,10 +1352,10 @@ void helper_mtc0_tchalt (target_ulong arg1) } } -void helper_mttc0_tchalt (target_ulong arg1) +void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); // TODO: Halt TC / Restart (if allocated+active) TC. @@ -1333,15 +1371,15 @@ void helper_mttc0_tchalt (target_ulong arg1) } } -void helper_mtc0_tccontext (target_ulong arg1) +void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCContext = arg1; } -void helper_mttc0_tccontext (target_ulong arg1) +void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCContext = arg1; @@ -1349,15 +1387,15 @@ void helper_mttc0_tccontext (target_ulong arg1) other->tcs[other_tc].CP0_TCContext = arg1; } -void helper_mtc0_tcschedule (target_ulong arg1) +void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCSchedule = arg1; } -void helper_mttc0_tcschedule (target_ulong arg1) +void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCSchedule = arg1; @@ -1365,15 +1403,15 @@ void helper_mttc0_tcschedule (target_ulong arg1) other->tcs[other_tc].CP0_TCSchedule = arg1; } -void helper_mtc0_tcschefback (target_ulong arg1) +void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCScheFBack = arg1; } -void helper_mttc0_tcschefback (target_ulong arg1) +void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCScheFBack = arg1; @@ -1381,25 +1419,25 @@ void helper_mttc0_tcschefback (target_ulong arg1) other->tcs[other_tc].CP0_TCScheFBack = arg1; } -void helper_mtc0_entrylo1 (target_ulong arg1) +void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) { /* Large physaddr (PABITS) not implemented */ /* 1k pages not implemented */ env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; } -void helper_mtc0_context (target_ulong arg1) +void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) { env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); } -void helper_mtc0_pagemask (target_ulong arg1) +void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) { /* 1k pages not implemented */ env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); } -void helper_mtc0_pagegrain (target_ulong arg1) +void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) { /* SmartMIPS not implemented */ /* Large physaddr (PABITS) not implemented */ @@ -1407,47 +1445,47 @@ void helper_mtc0_pagegrain (target_ulong arg1) env->CP0_PageGrain = 0; } -void helper_mtc0_wired (target_ulong arg1) +void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { env->CP0_Wired = arg1 % env->tlb->nb_tlb; } -void helper_mtc0_srsconf0 (target_ulong arg1) +void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; } -void helper_mtc0_srsconf1 (target_ulong arg1) +void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; } -void helper_mtc0_srsconf2 (target_ulong arg1) +void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; } -void helper_mtc0_srsconf3 (target_ulong arg1) +void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; } -void helper_mtc0_srsconf4 (target_ulong arg1) +void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; } -void helper_mtc0_hwrena (target_ulong arg1) +void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) { env->CP0_HWREna = arg1 & 0x0000000F; } -void helper_mtc0_count (target_ulong arg1) +void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) { cpu_mips_store_count(env, arg1); } -void helper_mtc0_entryhi (target_ulong arg1) +void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val; @@ -1466,21 +1504,21 @@ void helper_mtc0_entryhi (target_ulong arg1) cpu_mips_tlb_flush(env, 1); } -void helper_mttc0_entryhi(target_ulong arg1) +void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); other->CP0_EntryHi = arg1; sync_c0_entryhi(other, other_tc); } -void helper_mtc0_compare (target_ulong arg1) +void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) { cpu_mips_store_compare(env, arg1); } -void helper_mtc0_status (target_ulong arg1) +void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { uint32_t val, old; uint32_t mask = env->CP0_Status_rw_bitmask; @@ -1489,7 +1527,7 @@ void helper_mtc0_status (target_ulong arg1) old = env->CP0_Status; env->CP0_Status = (env->CP0_Status & ~mask) | val; if (env->CP0_Config3 & (1 << CP0C3_MT)) { - sync_c0_status(env, env->current_tc); + sync_c0_status(env, env, env->current_tc); } else { compute_hflags(env); } @@ -1508,22 +1546,22 @@ void helper_mtc0_status (target_ulong arg1) } } -void helper_mttc0_status(target_ulong arg1) +void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); other->CP0_Status = arg1 & ~0xf1000018; - sync_c0_status(other, other_tc); + sync_c0_status(env, other, other_tc); } -void helper_mtc0_intctl (target_ulong arg1) +void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) { /* vectored interrupts not implemented, no performance counters. */ env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); } -void helper_mtc0_srsctl (target_ulong arg1) +void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); @@ -1557,52 +1595,52 @@ static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) } } -void helper_mtc0_cause(target_ulong arg1) +void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) { mtc0_cause(env, arg1); } -void helper_mttc0_cause(target_ulong arg1) +void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); mtc0_cause(other, arg1); } -target_ulong helper_mftc0_epc(void) +target_ulong helper_mftc0_epc(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_EPC; } -target_ulong helper_mftc0_ebase(void) +target_ulong helper_mftc0_ebase(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_EBase; } -void helper_mtc0_ebase (target_ulong arg1) +void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) { /* vectored interrupts not implemented */ env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); } -void helper_mttc0_ebase(target_ulong arg1) +void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); } -target_ulong helper_mftc0_configx(target_ulong idx) +target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); switch (idx) { case 0: return other->CP0_Config0; @@ -1618,49 +1656,49 @@ target_ulong helper_mftc0_configx(target_ulong idx) return 0; } -void helper_mtc0_config0 (target_ulong arg1) +void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) { env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); } -void helper_mtc0_config2 (target_ulong arg1) +void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) { /* tertiary/secondary caches not implemented */ env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); } -void helper_mtc0_lladdr (target_ulong arg1) +void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) { target_long mask = env->CP0_LLAddr_rw_bitmask; arg1 = arg1 << env->CP0_LLAddr_shift; env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); } -void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel) +void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { /* Watch exceptions for instructions, data loads, data stores not implemented. */ env->CP0_WatchLo[sel] = (arg1 & ~0x7); } -void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel) +void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } -void helper_mtc0_xcontext (target_ulong arg1) +void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) { target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); } -void helper_mtc0_framemask (target_ulong arg1) +void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) { env->CP0_Framemask = arg1; /* XXX */ } -void helper_mtc0_debug (target_ulong arg1) +void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) { env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); if (arg1 & (1 << CP0DB_DM)) @@ -1669,11 +1707,11 @@ void helper_mtc0_debug (target_ulong arg1) env->hflags &= ~MIPS_HFLAG_DM; } -void helper_mttc0_debug(target_ulong arg1) +void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); /* XXX: Might be wrong, check with EJTAG spec. */ if (other_tc == other->current_tc) @@ -1685,36 +1723,36 @@ void helper_mttc0_debug(target_ulong arg1) (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); } -void helper_mtc0_performance0 (target_ulong arg1) +void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) { env->CP0_Performance0 = arg1 & 0x000007ff; } -void helper_mtc0_taglo (target_ulong arg1) +void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) { env->CP0_TagLo = arg1 & 0xFFFFFCF6; } -void helper_mtc0_datalo (target_ulong arg1) +void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) { env->CP0_DataLo = arg1; /* XXX */ } -void helper_mtc0_taghi (target_ulong arg1) +void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) { env->CP0_TagHi = arg1; /* XXX */ } -void helper_mtc0_datahi (target_ulong arg1) +void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) { env->CP0_DataHi = arg1; /* XXX */ } /* MIPS MT functions */ -target_ulong helper_mftgpr(uint32_t sel) +target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.gpr[sel]; @@ -1722,10 +1760,10 @@ target_ulong helper_mftgpr(uint32_t sel) return other->tcs[other_tc].gpr[sel]; } -target_ulong helper_mftlo(uint32_t sel) +target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.LO[sel]; @@ -1733,10 +1771,10 @@ target_ulong helper_mftlo(uint32_t sel) return other->tcs[other_tc].LO[sel]; } -target_ulong helper_mfthi(uint32_t sel) +target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.HI[sel]; @@ -1744,10 +1782,10 @@ target_ulong helper_mfthi(uint32_t sel) return other->tcs[other_tc].HI[sel]; } -target_ulong helper_mftacx(uint32_t sel) +target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.ACX[sel]; @@ -1755,10 +1793,10 @@ target_ulong helper_mftacx(uint32_t sel) return other->tcs[other_tc].ACX[sel]; } -target_ulong helper_mftdsp(void) +target_ulong helper_mftdsp(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.DSPControl; @@ -1766,10 +1804,10 @@ target_ulong helper_mftdsp(void) return other->tcs[other_tc].DSPControl; } -void helper_mttgpr(target_ulong arg1, uint32_t sel) +void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.gpr[sel] = arg1; @@ -1777,10 +1815,10 @@ void helper_mttgpr(target_ulong arg1, uint32_t sel) other->tcs[other_tc].gpr[sel] = arg1; } -void helper_mttlo(target_ulong arg1, uint32_t sel) +void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.LO[sel] = arg1; @@ -1788,10 +1826,10 @@ void helper_mttlo(target_ulong arg1, uint32_t sel) other->tcs[other_tc].LO[sel] = arg1; } -void helper_mtthi(target_ulong arg1, uint32_t sel) +void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.HI[sel] = arg1; @@ -1799,10 +1837,10 @@ void helper_mtthi(target_ulong arg1, uint32_t sel) other->tcs[other_tc].HI[sel] = arg1; } -void helper_mttacx(target_ulong arg1, uint32_t sel) +void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.ACX[sel] = arg1; @@ -1810,10 +1848,10 @@ void helper_mttacx(target_ulong arg1, uint32_t sel) other->tcs[other_tc].ACX[sel] = arg1; } -void helper_mttdsp(target_ulong arg1) +void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.DSPControl = arg1; @@ -1834,7 +1872,7 @@ target_ulong helper_emt(void) return 0; } -target_ulong helper_dvpe(void) +target_ulong helper_dvpe(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; @@ -1850,7 +1888,7 @@ target_ulong helper_dvpe(void) return prev; } -target_ulong helper_evpe(void) +target_ulong helper_evpe(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; @@ -1876,7 +1914,7 @@ void helper_fork(target_ulong arg1, target_ulong arg2) // TODO: store to TC register } -target_ulong helper_yield(target_ulong arg) +target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) { target_long arg1 = arg; @@ -1887,13 +1925,13 @@ target_ulong helper_yield(target_ulong arg) env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; - helper_raise_exception(EXCP_THREAD); + helper_raise_exception(env, EXCP_THREAD); } } } else if (arg1 == 0) { if (0 /* TODO: TC underflow */) { env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - helper_raise_exception(EXCP_THREAD); + helper_raise_exception(env, EXCP_THREAD); } else { // TODO: Deallocate TC } @@ -1901,7 +1939,7 @@ target_ulong helper_yield(target_ulong arg) /* Yield qualifier inputs not implemented. */ env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; - helper_raise_exception(EXCP_THREAD); + helper_raise_exception(env, EXCP_THREAD); } return env->CP0_YQMask; } @@ -1923,7 +1961,7 @@ static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) } } -static void r4k_fill_tlb (int idx) +static void r4k_fill_tlb(CPUMIPSState *env, int idx) { r4k_tlb_t *tlb; @@ -1946,7 +1984,7 @@ static void r4k_fill_tlb (int idx) tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; } -void r4k_helper_tlbwi (void) +void r4k_helper_tlbwi(CPUMIPSState *env) { int idx; @@ -1958,18 +1996,18 @@ void r4k_helper_tlbwi (void) r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); r4k_invalidate_tlb(env, idx, 0); - r4k_fill_tlb(idx); + r4k_fill_tlb(env, idx); } -void r4k_helper_tlbwr (void) +void r4k_helper_tlbwr(CPUMIPSState *env) { int r = cpu_mips_get_random(env); r4k_invalidate_tlb(env, r, 1); - r4k_fill_tlb(r); + r4k_fill_tlb(env, r); } -void r4k_helper_tlbp (void) +void r4k_helper_tlbp(CPUMIPSState *env) { r4k_tlb_t *tlb; target_ulong mask; @@ -2011,7 +2049,7 @@ void r4k_helper_tlbp (void) } } -void r4k_helper_tlbr (void) +void r4k_helper_tlbr(CPUMIPSState *env) { r4k_tlb_t *tlb; uint8_t ASID; @@ -2035,28 +2073,28 @@ void r4k_helper_tlbr (void) (tlb->C1 << 3) | (tlb->PFN[1] >> 6); } -void helper_tlbwi(void) +void helper_tlbwi(CPUMIPSState *env) { - env->tlb->helper_tlbwi(); + env->tlb->helper_tlbwi(env); } -void helper_tlbwr(void) +void helper_tlbwr(CPUMIPSState *env) { - env->tlb->helper_tlbwr(); + env->tlb->helper_tlbwr(env); } -void helper_tlbp(void) +void helper_tlbp(CPUMIPSState *env) { - env->tlb->helper_tlbp(); + env->tlb->helper_tlbp(env); } -void helper_tlbr(void) +void helper_tlbr(CPUMIPSState *env) { - env->tlb->helper_tlbr(); + env->tlb->helper_tlbr(env); } /* Specials */ -target_ulong helper_di (void) +target_ulong helper_di(CPUMIPSState *env) { target_ulong t0 = env->CP0_Status; @@ -2064,7 +2102,7 @@ target_ulong helper_di (void) return t0; } -target_ulong helper_ei (void) +target_ulong helper_ei(CPUMIPSState *env) { target_ulong t0 = env->CP0_Status; @@ -2072,7 +2110,7 @@ target_ulong helper_ei (void) return t0; } -static void debug_pre_eret (void) +static void debug_pre_eret(CPUMIPSState *env) { if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, @@ -2085,7 +2123,7 @@ static void debug_pre_eret (void) } } -static void debug_post_eret (void) +static void debug_post_eret(CPUMIPSState *env) { if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, @@ -2103,7 +2141,7 @@ static void debug_post_eret (void) } } -static void set_pc (target_ulong error_pc) +static void set_pc(CPUMIPSState *env, target_ulong error_pc) { env->active_tc.PC = error_pc & ~(target_ulong)1; if (error_pc & 1) { @@ -2113,78 +2151,78 @@ static void set_pc (target_ulong error_pc) } } -void helper_eret (void) +void helper_eret(CPUMIPSState *env) { - debug_pre_eret(); + debug_pre_eret(env); if (env->CP0_Status & (1 << CP0St_ERL)) { - set_pc(env->CP0_ErrorEPC); + set_pc(env, env->CP0_ErrorEPC); env->CP0_Status &= ~(1 << CP0St_ERL); } else { - set_pc(env->CP0_EPC); + set_pc(env, env->CP0_EPC); env->CP0_Status &= ~(1 << CP0St_EXL); } compute_hflags(env); - debug_post_eret(); + debug_post_eret(env); env->lladdr = 1; } -void helper_deret (void) +void helper_deret(CPUMIPSState *env) { - debug_pre_eret(); - set_pc(env->CP0_DEPC); + debug_pre_eret(env); + set_pc(env, env->CP0_DEPC); env->hflags &= MIPS_HFLAG_DM; compute_hflags(env); - debug_post_eret(); + debug_post_eret(env); env->lladdr = 1; } #endif /* !CONFIG_USER_ONLY */ -target_ulong helper_rdhwr_cpunum(void) +target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 0))) return env->CP0_EBase & 0x3ff; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -target_ulong helper_rdhwr_synci_step(void) +target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 1))) return env->SYNCI_Step; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -target_ulong helper_rdhwr_cc(void) +target_ulong helper_rdhwr_cc(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 2))) return env->CP0_Count; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -target_ulong helper_rdhwr_ccres(void) +target_ulong helper_rdhwr_ccres(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 3))) return env->CCRes; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -void helper_pmon (int function) +void helper_pmon(CPUMIPSState *env, int function) { function /= 2; switch (function) { @@ -2210,16 +2248,17 @@ void helper_pmon (int function) } } -void helper_wait (void) +void helper_wait(CPUMIPSState *env) { env->halted = 1; cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE); - helper_raise_exception(EXCP_HLT); + helper_raise_exception(env, EXCP_HLT); } #if !defined(CONFIG_USER_ONLY) -static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, +static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, + target_ulong addr, int is_write, int is_user, uintptr_t retaddr); #define MMUSUFFIX _mmu @@ -2237,23 +2276,20 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, #define SHIFT 3 #include "softmmu_template.h" -static void do_unaligned_access(target_ulong addr, int is_write, - int is_user, uintptr_t retaddr) +static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, + int is_write, int is_user, uintptr_t retaddr) { env->CP0_BadVAddr = addr; - do_restore_state (retaddr); - helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); + do_restore_state(env, retaddr); + helper_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL); } -void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { TranslationBlock *tb; - CPUMIPSState *saved_env; int ret; - saved_env = env; - env = env1; ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); if (ret) { if (retaddr) { @@ -2265,20 +2301,17 @@ void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx, cpu_restore_state(tb, env, retaddr); } } - helper_raise_exception_err(env->exception_index, env->error_code); + helper_raise_exception_err(env, env->exception_index, env->error_code); } - env = saved_env; } -void cpu_unassigned_access(CPUMIPSState *env1, target_phys_addr_t addr, +void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr, int is_write, int is_exec, int unused, int size) { - env = env1; - if (is_exec) - helper_raise_exception(EXCP_IBE); + helper_raise_exception(env, EXCP_IBE); else - helper_raise_exception(EXCP_DBE); + helper_raise_exception(env, EXCP_DBE); } #endif /* !CONFIG_USER_ONLY */ @@ -2307,7 +2340,7 @@ static unsigned int ieee_rm[] = { #define RESTORE_FLUSH_MODE \ set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); -target_ulong helper_cfc1 (uint32_t reg) +target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1; @@ -2332,7 +2365,7 @@ target_ulong helper_cfc1 (uint32_t reg) return arg1; } -void helper_ctc1 (target_ulong arg1, uint32_t reg) +void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg) { switch(reg) { case 25: @@ -2366,7 +2399,7 @@ void helper_ctc1 (target_ulong arg1, uint32_t reg) RESTORE_FLUSH_MODE; set_float_exception_flags(0, &env->active_fpu.fp_status); if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) - helper_raise_exception(EXCP_FPE); + helper_raise_exception(env, EXCP_FPE); } static inline int ieee_ex_to_mips(int xcpt) @@ -2392,13 +2425,13 @@ static inline int ieee_ex_to_mips(int xcpt) return ret; } -static inline void update_fcr31(void) +static inline void update_fcr31(CPUMIPSState *env) { int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); SET_FP_CAUSE(env->active_fpu.fcr31, tmp); if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) - helper_raise_exception(EXCP_FPE); + helper_raise_exception(env, EXCP_FPE); else UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); } @@ -2409,71 +2442,71 @@ static inline void update_fcr31(void) paired single lower "pl", paired single upper "pu". */ /* unary operations, modifying fp status */ -uint64_t helper_float_sqrt_d(uint64_t fdt0) +uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) { return float64_sqrt(fdt0, &env->active_fpu.fp_status); } -uint32_t helper_float_sqrt_s(uint32_t fst0) +uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) { return float32_sqrt(fst0, &env->active_fpu.fp_status); } -uint64_t helper_float_cvtd_s(uint32_t fst0) +uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint64_t helper_float_cvtd_w(uint32_t wt0) +uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint64_t helper_float_cvtd_l(uint64_t dt0) +uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint64_t helper_float_cvtl_d(uint64_t fdt0) +uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_cvtl_s(uint32_t fst0) +uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_cvtps_pw(uint64_t dt0) +uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) { uint32_t fst2; uint32_t fsth2; @@ -2481,11 +2514,11 @@ uint64_t helper_float_cvtps_pw(uint64_t dt0) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_cvtpw_ps(uint64_t fdt0) +uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; uint32_t wth2; @@ -2493,7 +2526,7 @@ uint64_t helper_float_cvtpw_ps(uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { wt2 = FLOAT_SNAN32; wth2 = FLOAT_SNAN32; @@ -2501,81 +2534,81 @@ uint64_t helper_float_cvtpw_ps(uint64_t fdt0) return ((uint64_t)wth2 << 32) | wt2; } -uint32_t helper_float_cvts_d(uint64_t fdt0) +uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint32_t helper_float_cvts_w(uint32_t wt0) +uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint32_t helper_float_cvts_l(uint64_t dt0) +uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint32_t helper_float_cvts_pl(uint32_t wt0) +uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = wt0; - update_fcr31(); + update_fcr31(env); return wt2; } -uint32_t helper_float_cvts_pu(uint32_t wth0) +uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = wth0; - update_fcr31(); + update_fcr31(env); return wt2; } -uint32_t helper_float_cvtw_s(uint32_t fst0) +uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_cvtw_d(uint64_t fdt0) +uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_roundl_d(uint64_t fdt0) +uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; @@ -2583,13 +2616,13 @@ uint64_t helper_float_roundl_d(uint64_t fdt0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_roundl_s(uint32_t fst0) +uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; @@ -2597,13 +2630,13 @@ uint64_t helper_float_roundl_s(uint32_t fst0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_roundw_d(uint64_t fdt0) +uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; @@ -2611,13 +2644,13 @@ uint32_t helper_float_roundw_d(uint64_t fdt0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_roundw_s(uint32_t fst0) +uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; @@ -2625,61 +2658,61 @@ uint32_t helper_float_roundw_s(uint32_t fst0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_truncl_d(uint64_t fdt0) +uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_truncl_s(uint32_t fst0) +uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_truncw_d(uint64_t fdt0) +uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_truncw_s(uint32_t fst0) +uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_ceill_d(uint64_t fdt0) +uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; @@ -2687,13 +2720,13 @@ uint64_t helper_float_ceill_d(uint64_t fdt0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_ceill_s(uint32_t fst0) +uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; @@ -2701,13 +2734,13 @@ uint64_t helper_float_ceill_s(uint32_t fst0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_ceilw_d(uint64_t fdt0) +uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; @@ -2715,13 +2748,13 @@ uint32_t helper_float_ceilw_d(uint64_t fdt0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_ceilw_s(uint32_t fst0) +uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; @@ -2729,13 +2762,13 @@ uint32_t helper_float_ceilw_s(uint32_t fst0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_floorl_d(uint64_t fdt0) +uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; @@ -2743,13 +2776,13 @@ uint64_t helper_float_floorl_d(uint64_t fdt0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_floorl_s(uint32_t fst0) +uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; @@ -2757,13 +2790,13 @@ uint64_t helper_float_floorl_s(uint32_t fst0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_floorw_d(uint64_t fdt0) +uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; @@ -2771,13 +2804,13 @@ uint32_t helper_float_floorw_d(uint64_t fdt0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_floorw_s(uint32_t fst0) +uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; @@ -2785,7 +2818,7 @@ uint32_t helper_float_floorw_s(uint32_t fst0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; @@ -2815,69 +2848,69 @@ FLOAT_UNOP(chs) #undef FLOAT_UNOP /* MIPS specific unary operations */ -uint64_t helper_float_recip_d(uint64_t fdt0) +uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_recip_s(uint32_t fst0) +uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_rsqrt_d(uint64_t fdt0) +uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_rsqrt_s(uint32_t fst0) +uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_recip1_d(uint64_t fdt0) +uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_recip1_s(uint32_t fst0) +uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_recip1_ps(uint64_t fdt0) +uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t fst2; uint32_t fsth2; @@ -2885,33 +2918,33 @@ uint64_t helper_float_recip1_ps(uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_rsqrt1_d(uint64_t fdt0) +uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_rsqrt1_s(uint32_t fst0) +uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) +uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t fst2; uint32_t fsth2; @@ -2921,39 +2954,43 @@ uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -#define FLOAT_OP(name, p) void helper_float_##name##_##p(void) +#define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env) /* binary operations */ #define FLOAT_BINOP(name) \ -uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ +uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ + uint64_t fdt0, uint64_t fdt1) \ { \ uint64_t dt2; \ \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ - update_fcr31(); \ + update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ dt2 = FLOAT_QNAN64; \ return dt2; \ } \ \ -uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ +uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ + uint32_t fst0, uint32_t fst1) \ { \ uint32_t wt2; \ \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ - update_fcr31(); \ + update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ wt2 = FLOAT_QNAN32; \ return wt2; \ } \ \ -uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ +uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1) \ { \ uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ uint32_t fsth0 = fdt0 >> 32; \ @@ -2965,7 +3002,7 @@ uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ - update_fcr31(); \ + update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ wt2 = FLOAT_QNAN32; \ wth2 = FLOAT_QNAN32; \ @@ -2981,22 +3018,28 @@ FLOAT_BINOP(div) /* ternary operations */ #define FLOAT_TERNOP(name1, name2) \ -uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ +uint64_t helper_float_ ## name1 ## name2 ## _d(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ } \ \ -uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ - uint32_t fst2) \ +uint32_t helper_float_ ## name1 ## name2 ## _s(CPUMIPSState *env, \ + uint32_t fst0, \ + uint32_t fst1, \ + uint32_t fst2) \ { \ fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ } \ \ -uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ +uint64_t helper_float_ ## name1 ## name2 ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ uint32_t fsth0 = fdt0 >> 32; \ @@ -3018,24 +3061,30 @@ FLOAT_TERNOP(mul, sub) /* negated ternary operations */ #define FLOAT_NTERNOP(name1, name2) \ -uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ +uint64_t helper_float_n ## name1 ## name2 ## _d(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ return float64_chs(fdt2); \ } \ \ -uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ - uint32_t fst2) \ +uint32_t helper_float_n ## name1 ## name2 ## _s(CPUMIPSState *env, \ + uint32_t fst0, \ + uint32_t fst1, \ + uint32_t fst2) \ { \ fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ return float32_chs(fst2); \ } \ \ -uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ - uint64_t fdt2) \ +uint64_t helper_float_n ## name1 ## name2 ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ uint32_t fsth0 = fdt0 >> 32; \ @@ -3058,25 +3107,25 @@ FLOAT_NTERNOP(mul, sub) #undef FLOAT_NTERNOP /* MIPS specific binary operations */ -uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2) +uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3088,31 +3137,31 @@ uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) +uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3126,11 +3175,11 @@ uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) +uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3142,11 +3191,11 @@ uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) +uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3158,31 +3207,33 @@ uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } /* compare operations */ #define FOP_COND_D(op, cond) \ -void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ CLEAR_FP_COND(cc, env->active_fpu); \ } \ -void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ fdt0 = float64_abs(fdt0); \ fdt1 = float64_abs(fdt1); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3211,25 +3262,27 @@ FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) #define FOP_COND_S(op, cond) \ -void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ CLEAR_FP_COND(cc, env->active_fpu); \ } \ -void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ fst0 = float32_abs(fst0); \ fst1 = float32_abs(fst1); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3258,7 +3311,8 @@ FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) #define FOP_COND_PS(op, condl, condh) \ -void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ uint32_t fst0, fsth0, fst1, fsth1; \ int ch, cl; \ @@ -3269,7 +3323,7 @@ void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ fsth1 = fdt1 >> 32; \ cl = condl; \ ch = condh; \ - update_fcr31(); \ + update_fcr31(env); \ if (cl) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3279,7 +3333,8 @@ void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ else \ CLEAR_FP_COND(cc + 1, env->active_fpu); \ } \ -void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ uint32_t fst0, fsth0, fst1, fsth1; \ int ch, cl; \ @@ -3289,7 +3344,7 @@ void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ fsth1 = float32_abs(fdt1 >> 32); \ cl = condl; \ ch = condh; \ - update_fcr31(); \ + update_fcr31(env); \ if (cl) \ SET_FP_COND(cc, env->active_fpu); \ else \ diff --git a/target-mips/translate.c b/target-mips/translate.c index a884f751bc..52eeb2bf79 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -483,27 +483,45 @@ static uint32_t gen_opc_hflags[OPC_BUF_SIZE]; #include "gen-icount.h" -#define gen_helper_0i(name, arg) do { \ +#define gen_helper_0e0i(name, arg) do { \ TCGv_i32 helper_tmp = tcg_const_i32(arg); \ - gen_helper_##name(helper_tmp); \ + gen_helper_##name(cpu_env, helper_tmp); \ tcg_temp_free_i32(helper_tmp); \ } while(0) -#define gen_helper_1i(name, arg1, arg2) do { \ +#define gen_helper_0e1i(name, arg1, arg2) do { \ TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ - gen_helper_##name(arg1, helper_tmp); \ + gen_helper_##name(cpu_env, arg1, helper_tmp); \ tcg_temp_free_i32(helper_tmp); \ } while(0) -#define gen_helper_2i(name, arg1, arg2, arg3) do { \ +#define gen_helper_1e0i(name, ret, arg1) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg1); \ + gen_helper_##name(ret, cpu_env, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_1e1i(name, ret, arg1, arg2) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ + gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ + gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \ TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ - gen_helper_##name(arg1, arg2, helper_tmp); \ + gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \ tcg_temp_free_i32(helper_tmp); \ } while(0) -#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \ +#define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \ TCGv_i32 helper_tmp = tcg_const_i32(arg4); \ - gen_helper_##name(arg1, arg2, arg3, helper_tmp); \ + gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \ tcg_temp_free_i32(helper_tmp); \ } while(0) @@ -748,7 +766,7 @@ generate_exception_err (DisasContext *ctx, int excp, int err) TCGv_i32 texcp = tcg_const_i32(excp); TCGv_i32 terr = tcg_const_i32(err); save_cpu_state(ctx, 1); - gen_helper_raise_exception_err(texcp, terr); + gen_helper_raise_exception_err(cpu_env, texcp, terr); tcg_temp_free_i32(terr); tcg_temp_free_i32(texcp); } @@ -757,7 +775,7 @@ static inline void generate_exception (DisasContext *ctx, int excp) { save_cpu_state(ctx, 1); - gen_helper_0i(raise_exception, excp); + gen_helper_0e0i(raise_exception, excp); } /* Addresses computation */ @@ -871,22 +889,22 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ gen_ldcmp_fpr##bits (ctx, fp0, fs); \ gen_ldcmp_fpr##bits (ctx, fp1, ft); \ switch (n) { \ - case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\ - case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\ - case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\ - case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\ - case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\ - case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\ - case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\ - case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\ - case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\ - case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\ - case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\ - case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\ - case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\ - case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\ - case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\ - case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\ + case 0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\ + case 1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\ + case 2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\ + case 3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\ + case 4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\ + case 5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\ + case 6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\ + case 7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\ + case 8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\ + case 9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\ + case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\ + case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\ + case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\ + case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\ + case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\ + case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\ default: abort(); \ } \ tcg_temp_free_i##bits (fp0); \ @@ -948,7 +966,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ #define OP_LD_ATOMIC(insn,fname) \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ { \ - gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \ + gen_helper_1e1i(insn, ret, arg1, ctx->mem_idx); \ } #endif OP_LD_ATOMIC(ll,ld32s); @@ -975,7 +993,7 @@ static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \ tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \ - gen_helper_0i(raise_exception, EXCP_SC); \ + gen_helper_0e0i(raise_exception, EXCP_SC); \ gen_set_label(l2); \ tcg_gen_movi_tl(t0, 0); \ gen_store_gpr(t0, rt); \ @@ -986,7 +1004,7 @@ static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ { \ TCGv t0 = tcg_temp_new(); \ - gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \ + gen_helper_1e2i(insn, t0, arg1, arg2, ctx->mem_idx); \ gen_store_gpr(t0, rt); \ tcg_temp_free(t0); \ } @@ -1066,14 +1084,14 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, case OPC_LDL: save_cpu_state(ctx, 1); gen_load_gpr(t1, rt); - gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx); + gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); opn = "ldl"; break; case OPC_LDR: save_cpu_state(ctx, 1); gen_load_gpr(t1, rt); - gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx); + gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); opn = "ldr"; break; @@ -1127,14 +1145,14 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, case OPC_LWL: save_cpu_state(ctx, 1); gen_load_gpr(t1, rt); - gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx); + gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); opn = "lwl"; break; case OPC_LWR: save_cpu_state(ctx, 1); gen_load_gpr(t1, rt); - gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx); + gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); opn = "lwr"; break; @@ -1170,12 +1188,12 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, break; case OPC_SDL: save_cpu_state(ctx, 1); - gen_helper_2i(sdl, t1, t0, ctx->mem_idx); + gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); opn = "sdl"; break; case OPC_SDR: save_cpu_state(ctx, 1); - gen_helper_2i(sdr, t1, t0, ctx->mem_idx); + gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); opn = "sdr"; break; #endif @@ -1196,12 +1214,12 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, break; case OPC_SWL: save_cpu_state(ctx, 1); - gen_helper_2i(swl, t1, t0, ctx->mem_idx); + gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); opn = "swl"; break; case OPC_SWR: save_cpu_state(ctx, 1); - gen_helper_2i(swr, t1, t0, ctx->mem_idx); + gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); opn = "swr"; break; } @@ -2138,11 +2156,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, opn = "ddivu"; break; case OPC_DMULT: - gen_helper_dmult(t0, t1); + gen_helper_dmult(cpu_env, t0, t1); opn = "dmult"; break; case OPC_DMULTU: - gen_helper_dmultu(t0, t1); + gen_helper_dmultu(cpu_env, t0, t1); opn = "dmultu"; break; #endif @@ -2254,59 +2272,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, switch (opc) { case OPC_VR54XX_MULS: - gen_helper_muls(t0, t0, t1); + gen_helper_muls(t0, cpu_env, t0, t1); opn = "muls"; break; case OPC_VR54XX_MULSU: - gen_helper_mulsu(t0, t0, t1); + gen_helper_mulsu(t0, cpu_env, t0, t1); opn = "mulsu"; break; case OPC_VR54XX_MACC: - gen_helper_macc(t0, t0, t1); + gen_helper_macc(t0, cpu_env, t0, t1); opn = "macc"; break; case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, t0, t1); + gen_helper_maccu(t0, cpu_env, t0, t1); opn = "maccu"; break; case OPC_VR54XX_MSAC: - gen_helper_msac(t0, t0, t1); + gen_helper_msac(t0, cpu_env, t0, t1); opn = "msac"; break; case OPC_VR54XX_MSACU: - gen_helper_msacu(t0, t0, t1); + gen_helper_msacu(t0, cpu_env, t0, t1); opn = "msacu"; break; case OPC_VR54XX_MULHI: - gen_helper_mulhi(t0, t0, t1); + gen_helper_mulhi(t0, cpu_env, t0, t1); opn = "mulhi"; break; case OPC_VR54XX_MULHIU: - gen_helper_mulhiu(t0, t0, t1); + gen_helper_mulhiu(t0, cpu_env, t0, t1); opn = "mulhiu"; break; case OPC_VR54XX_MULSHI: - gen_helper_mulshi(t0, t0, t1); + gen_helper_mulshi(t0, cpu_env, t0, t1); opn = "mulshi"; break; case OPC_VR54XX_MULSHIU: - gen_helper_mulshiu(t0, t0, t1); + gen_helper_mulshiu(t0, cpu_env, t0, t1); opn = "mulshiu"; break; case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, t0, t1); + gen_helper_macchi(t0, cpu_env, t0, t1); opn = "macchi"; break; case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, t0, t1); + gen_helper_macchiu(t0, cpu_env, t0, t1); opn = "macchiu"; break; case OPC_VR54XX_MSACHI: - gen_helper_msachi(t0, t0, t1); + gen_helper_msachi(t0, cpu_env, t0, t1); opn = "msachi"; break; case OPC_VR54XX_MSACHIU: - gen_helper_msachiu(t0, t0, t1); + gen_helper_msachiu(t0, cpu_env, t0, t1); opn = "msachiu"; break; default: @@ -2683,7 +2701,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) gen_save_pc(dest); if (ctx->singlestep_enabled) { save_cpu_state(ctx, 0); - gen_helper_0i(raise_exception, EXCP_DEBUG); + gen_helper_0e0i(raise_exception, EXCP_DEBUG); } tcg_gen_exit_tb(0); } @@ -3187,17 +3205,17 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_mvpcontrol(arg); + gen_helper_mfc0_mvpcontrol(arg, cpu_env); rn = "MVPControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_mvpconf0(arg); + gen_helper_mfc0_mvpconf0(arg, cpu_env); rn = "MVPConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_mvpconf1(arg); + gen_helper_mfc0_mvpconf1(arg, cpu_env); rn = "MVPConf1"; break; default: @@ -3207,7 +3225,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 1: switch (sel) { case 0: - gen_helper_mfc0_random(arg); + gen_helper_mfc0_random(arg, cpu_env); rn = "Random"; break; case 1: @@ -3258,37 +3276,37 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tcstatus(arg); + gen_helper_mfc0_tcstatus(arg, cpu_env); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tcbind(arg); + gen_helper_mfc0_tcbind(arg, cpu_env); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tcrestart(arg); + gen_helper_mfc0_tcrestart(arg, cpu_env); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tchalt(arg); + gen_helper_mfc0_tchalt(arg, cpu_env); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tccontext(arg); + gen_helper_mfc0_tccontext(arg, cpu_env); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tcschedule(arg); + gen_helper_mfc0_tcschedule(arg, cpu_env); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tcschefback(arg); + gen_helper_mfc0_tcschefback(arg, cpu_env); rn = "TCScheFBack"; break; default: @@ -3399,7 +3417,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i /* Mark as an IO operation because we read the time. */ if (use_icount) gen_io_start(); - gen_helper_mfc0_count(arg); + gen_helper_mfc0_count(arg, cpu_env); if (use_icount) { gen_io_end(); } @@ -3531,7 +3549,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 17: switch (sel) { case 0: - gen_helper_mfc0_lladdr(arg); + gen_helper_mfc0_lladdr(arg, cpu_env); rn = "LLAddr"; break; default: @@ -3541,7 +3559,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 18: switch (sel) { case 0 ... 7: - gen_helper_1i(mfc0_watchlo, arg, sel); + gen_helper_1e0i(mfc0_watchlo, arg, sel); rn = "WatchLo"; break; default: @@ -3551,7 +3569,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 19: switch (sel) { case 0 ...7: - gen_helper_1i(mfc0_watchhi, arg, sel); + gen_helper_1e0i(mfc0_watchhi, arg, sel); rn = "WatchHi"; break; default: @@ -3590,7 +3608,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 23: switch (sel) { case 0: - gen_helper_mfc0_debug(arg); /* EJTAG support */ + gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ rn = "Debug"; break; case 1: @@ -3765,12 +3783,12 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 0: switch (sel) { case 0: - gen_helper_mtc0_index(arg); + gen_helper_mtc0_index(cpu_env, arg); rn = "Index"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_mvpcontrol(arg); + gen_helper_mtc0_mvpcontrol(cpu_env, arg); rn = "MVPControl"; break; case 2: @@ -3795,22 +3813,22 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpecontrol(arg); + gen_helper_mtc0_vpecontrol(cpu_env, arg); rn = "VPEControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpeconf0(arg); + gen_helper_mtc0_vpeconf0(cpu_env, arg); rn = "VPEConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpeconf1(arg); + gen_helper_mtc0_vpeconf1(cpu_env, arg); rn = "VPEConf1"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_yqmask(arg); + gen_helper_mtc0_yqmask(cpu_env, arg); rn = "YQMask"; break; case 5: @@ -3825,7 +3843,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i break; case 7: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpeopt(arg); + gen_helper_mtc0_vpeopt(cpu_env, arg); rn = "VPEOpt"; break; default: @@ -3835,42 +3853,42 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 2: switch (sel) { case 0: - gen_helper_mtc0_entrylo0(arg); + gen_helper_mtc0_entrylo0(cpu_env, arg); rn = "EntryLo0"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcstatus(arg); + gen_helper_mtc0_tcstatus(cpu_env, arg); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcbind(arg); + gen_helper_mtc0_tcbind(cpu_env, arg); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcrestart(arg); + gen_helper_mtc0_tcrestart(cpu_env, arg); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tchalt(arg); + gen_helper_mtc0_tchalt(cpu_env, arg); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tccontext(arg); + gen_helper_mtc0_tccontext(cpu_env, arg); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcschedule(arg); + gen_helper_mtc0_tcschedule(cpu_env, arg); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcschefback(arg); + gen_helper_mtc0_tcschefback(cpu_env, arg); rn = "TCScheFBack"; break; default: @@ -3880,7 +3898,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 3: switch (sel) { case 0: - gen_helper_mtc0_entrylo1(arg); + gen_helper_mtc0_entrylo1(cpu_env, arg); rn = "EntryLo1"; break; default: @@ -3890,11 +3908,11 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 4: switch (sel) { case 0: - gen_helper_mtc0_context(arg); + gen_helper_mtc0_context(cpu_env, arg); rn = "Context"; break; case 1: -// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ +// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */ rn = "ContextConfig"; // break; default: @@ -3904,12 +3922,12 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 5: switch (sel) { case 0: - gen_helper_mtc0_pagemask(arg); + gen_helper_mtc0_pagemask(cpu_env, arg); rn = "PageMask"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_pagegrain(arg); + gen_helper_mtc0_pagegrain(cpu_env, arg); rn = "PageGrain"; break; default: @@ -3919,32 +3937,32 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 6: switch (sel) { case 0: - gen_helper_mtc0_wired(arg); + gen_helper_mtc0_wired(cpu_env, arg); rn = "Wired"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf0(arg); + gen_helper_mtc0_srsconf0(cpu_env, arg); rn = "SRSConf0"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf1(arg); + gen_helper_mtc0_srsconf1(cpu_env, arg); rn = "SRSConf1"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf2(arg); + gen_helper_mtc0_srsconf2(cpu_env, arg); rn = "SRSConf2"; break; case 4: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf3(arg); + gen_helper_mtc0_srsconf3(cpu_env, arg); rn = "SRSConf3"; break; case 5: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf4(arg); + gen_helper_mtc0_srsconf4(cpu_env, arg); rn = "SRSConf4"; break; default: @@ -3955,7 +3973,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i switch (sel) { case 0: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_hwrena(arg); + gen_helper_mtc0_hwrena(cpu_env, arg); rn = "HWREna"; break; default: @@ -3969,7 +3987,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 9: switch (sel) { case 0: - gen_helper_mtc0_count(arg); + gen_helper_mtc0_count(cpu_env, arg); rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -3980,7 +3998,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 10: switch (sel) { case 0: - gen_helper_mtc0_entryhi(arg); + gen_helper_mtc0_entryhi(cpu_env, arg); rn = "EntryHi"; break; default: @@ -3990,7 +4008,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 11: switch (sel) { case 0: - gen_helper_mtc0_compare(arg); + gen_helper_mtc0_compare(cpu_env, arg); rn = "Compare"; break; /* 6,7 are implementation dependent */ @@ -4002,7 +4020,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i switch (sel) { case 0: save_cpu_state(ctx, 1); - gen_helper_mtc0_status(arg); + gen_helper_mtc0_status(cpu_env, arg); /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; @@ -4010,14 +4028,14 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_intctl(arg); + gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsctl(arg); + gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSCtl"; @@ -4037,7 +4055,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i switch (sel) { case 0: save_cpu_state(ctx, 1); - gen_helper_mtc0_cause(arg); + gen_helper_mtc0_cause(cpu_env, arg); rn = "Cause"; break; default: @@ -4062,7 +4080,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_ebase(arg); + gen_helper_mtc0_ebase(cpu_env, arg); rn = "EBase"; break; default: @@ -4072,7 +4090,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 16: switch (sel) { case 0: - gen_helper_mtc0_config0(arg); + gen_helper_mtc0_config0(cpu_env, arg); rn = "Config"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -4082,7 +4100,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i rn = "Config1"; break; case 2: - gen_helper_mtc0_config2(arg); + gen_helper_mtc0_config2(cpu_env, arg); rn = "Config2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -4109,7 +4127,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 17: switch (sel) { case 0: - gen_helper_mtc0_lladdr(arg); + gen_helper_mtc0_lladdr(cpu_env, arg); rn = "LLAddr"; break; default: @@ -4119,7 +4137,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 18: switch (sel) { case 0 ... 7: - gen_helper_1i(mtc0_watchlo, arg, sel); + gen_helper_0e1i(mtc0_watchlo, arg, sel); rn = "WatchLo"; break; default: @@ -4129,7 +4147,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 19: switch (sel) { case 0 ... 7: - gen_helper_1i(mtc0_watchhi, arg, sel); + gen_helper_0e1i(mtc0_watchhi, arg, sel); rn = "WatchHi"; break; default: @@ -4141,7 +4159,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 0: #if defined(TARGET_MIPS64) check_insn(env, ctx, ISA_MIPS3); - gen_helper_mtc0_xcontext(arg); + gen_helper_mtc0_xcontext(cpu_env, arg); rn = "XContext"; break; #endif @@ -4153,7 +4171,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i /* Officially reserved, but sel 0 is used for R1x000 framemask */ switch (sel) { case 0: - gen_helper_mtc0_framemask(arg); + gen_helper_mtc0_framemask(cpu_env, arg); rn = "Framemask"; break; default: @@ -4167,20 +4185,20 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 23: switch (sel) { case 0: - gen_helper_mtc0_debug(arg); /* EJTAG support */ + gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; rn = "Debug"; break; case 1: -// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ +// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */ rn = "TraceControl"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // break; case 2: -// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ +// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */ rn = "TraceControl2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -4188,13 +4206,13 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 3: /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; -// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ +// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */ rn = "UserTraceData"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // break; case 4: -// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ +// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceBPC"; @@ -4217,7 +4235,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 25: switch (sel) { case 0: - gen_helper_mtc0_performance0(arg); + gen_helper_mtc0_performance0(cpu_env, arg); rn = "Performance0"; break; case 1: @@ -4272,14 +4290,14 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 2: case 4: case 6: - gen_helper_mtc0_taglo(arg); + gen_helper_mtc0_taglo(cpu_env, arg); rn = "TagLo"; break; case 1: case 3: case 5: case 7: - gen_helper_mtc0_datalo(arg); + gen_helper_mtc0_datalo(cpu_env, arg); rn = "DataLo"; break; default: @@ -4292,14 +4310,14 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i case 2: case 4: case 6: - gen_helper_mtc0_taghi(arg); + gen_helper_mtc0_taghi(cpu_env, arg); rn = "TagHi"; break; case 1: case 3: case 5: case 7: - gen_helper_mtc0_datahi(arg); + gen_helper_mtc0_datahi(cpu_env, arg); rn = "DataHi"; break; default: @@ -4364,17 +4382,17 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_mvpcontrol(arg); + gen_helper_mfc0_mvpcontrol(arg, cpu_env); rn = "MVPControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_mvpconf0(arg); + gen_helper_mfc0_mvpconf0(arg, cpu_env); rn = "MVPConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_mvpconf1(arg); + gen_helper_mfc0_mvpconf1(arg, cpu_env); rn = "MVPConf1"; break; default: @@ -4384,7 +4402,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 1: switch (sel) { case 0: - gen_helper_mfc0_random(arg); + gen_helper_mfc0_random(arg, cpu_env); rn = "Random"; break; case 1: @@ -4434,37 +4452,37 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tcstatus(arg); + gen_helper_mfc0_tcstatus(arg, cpu_env); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mfc0_tcbind(arg); + gen_helper_mfc0_tcbind(arg, cpu_env); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_dmfc0_tcrestart(arg); + gen_helper_dmfc0_tcrestart(arg, cpu_env); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_helper_dmfc0_tchalt(arg); + gen_helper_dmfc0_tchalt(arg, cpu_env); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_helper_dmfc0_tccontext(arg); + gen_helper_dmfc0_tccontext(arg, cpu_env); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_helper_dmfc0_tcschedule(arg); + gen_helper_dmfc0_tcschedule(arg, cpu_env); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_helper_dmfc0_tcschefback(arg); + gen_helper_dmfc0_tcschefback(arg, cpu_env); rn = "TCScheFBack"; break; default: @@ -4572,7 +4590,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, /* Mark as an IO operation because we read the time. */ if (use_icount) gen_io_start(); - gen_helper_mfc0_count(arg); + gen_helper_mfc0_count(arg, cpu_env); if (use_icount) { gen_io_end(); } @@ -4701,7 +4719,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 17: switch (sel) { case 0: - gen_helper_dmfc0_lladdr(arg); + gen_helper_dmfc0_lladdr(arg, cpu_env); rn = "LLAddr"; break; default: @@ -4711,7 +4729,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 18: switch (sel) { case 0 ... 7: - gen_helper_1i(dmfc0_watchlo, arg, sel); + gen_helper_1e0i(dmfc0_watchlo, arg, sel); rn = "WatchLo"; break; default: @@ -4721,7 +4739,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 19: switch (sel) { case 0 ... 7: - gen_helper_1i(mfc0_watchhi, arg, sel); + gen_helper_1e0i(mfc0_watchhi, arg, sel); rn = "WatchHi"; break; default: @@ -4757,23 +4775,23 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 23: switch (sel) { case 0: - gen_helper_mfc0_debug(arg); /* EJTAG support */ + gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ rn = "Debug"; break; case 1: -// gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */ +// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */ rn = "TraceControl"; // break; case 2: -// gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */ +// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */ rn = "TraceControl2"; // break; case 3: -// gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */ +// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */ rn = "UserTraceData"; // break; case 4: -// gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */ +// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */ rn = "TraceBPC"; // break; default: @@ -4931,12 +4949,12 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 0: switch (sel) { case 0: - gen_helper_mtc0_index(arg); + gen_helper_mtc0_index(cpu_env, arg); rn = "Index"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_mvpcontrol(arg); + gen_helper_mtc0_mvpcontrol(cpu_env, arg); rn = "MVPControl"; break; case 2: @@ -4961,22 +4979,22 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpecontrol(arg); + gen_helper_mtc0_vpecontrol(cpu_env, arg); rn = "VPEControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpeconf0(arg); + gen_helper_mtc0_vpeconf0(cpu_env, arg); rn = "VPEConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpeconf1(arg); + gen_helper_mtc0_vpeconf1(cpu_env, arg); rn = "VPEConf1"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_yqmask(arg); + gen_helper_mtc0_yqmask(cpu_env, arg); rn = "YQMask"; break; case 5: @@ -4991,7 +5009,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, break; case 7: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_vpeopt(arg); + gen_helper_mtc0_vpeopt(cpu_env, arg); rn = "VPEOpt"; break; default: @@ -5001,42 +5019,42 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 2: switch (sel) { case 0: - gen_helper_mtc0_entrylo0(arg); + gen_helper_mtc0_entrylo0(cpu_env, arg); rn = "EntryLo0"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcstatus(arg); + gen_helper_mtc0_tcstatus(cpu_env, arg); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcbind(arg); + gen_helper_mtc0_tcbind(cpu_env, arg); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcrestart(arg); + gen_helper_mtc0_tcrestart(cpu_env, arg); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tchalt(arg); + gen_helper_mtc0_tchalt(cpu_env, arg); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tccontext(arg); + gen_helper_mtc0_tccontext(cpu_env, arg); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcschedule(arg); + gen_helper_mtc0_tcschedule(cpu_env, arg); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_helper_mtc0_tcschefback(arg); + gen_helper_mtc0_tcschefback(cpu_env, arg); rn = "TCScheFBack"; break; default: @@ -5046,7 +5064,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 3: switch (sel) { case 0: - gen_helper_mtc0_entrylo1(arg); + gen_helper_mtc0_entrylo1(cpu_env, arg); rn = "EntryLo1"; break; default: @@ -5056,11 +5074,11 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 4: switch (sel) { case 0: - gen_helper_mtc0_context(arg); + gen_helper_mtc0_context(cpu_env, arg); rn = "Context"; break; case 1: -// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ +// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */ rn = "ContextConfig"; // break; default: @@ -5070,12 +5088,12 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 5: switch (sel) { case 0: - gen_helper_mtc0_pagemask(arg); + gen_helper_mtc0_pagemask(cpu_env, arg); rn = "PageMask"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_pagegrain(arg); + gen_helper_mtc0_pagegrain(cpu_env, arg); rn = "PageGrain"; break; default: @@ -5085,32 +5103,32 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 6: switch (sel) { case 0: - gen_helper_mtc0_wired(arg); + gen_helper_mtc0_wired(cpu_env, arg); rn = "Wired"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf0(arg); + gen_helper_mtc0_srsconf0(cpu_env, arg); rn = "SRSConf0"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf1(arg); + gen_helper_mtc0_srsconf1(cpu_env, arg); rn = "SRSConf1"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf2(arg); + gen_helper_mtc0_srsconf2(cpu_env, arg); rn = "SRSConf2"; break; case 4: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf3(arg); + gen_helper_mtc0_srsconf3(cpu_env, arg); rn = "SRSConf3"; break; case 5: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsconf4(arg); + gen_helper_mtc0_srsconf4(cpu_env, arg); rn = "SRSConf4"; break; default: @@ -5121,7 +5139,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, switch (sel) { case 0: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_hwrena(arg); + gen_helper_mtc0_hwrena(cpu_env, arg); rn = "HWREna"; break; default: @@ -5135,7 +5153,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 9: switch (sel) { case 0: - gen_helper_mtc0_count(arg); + gen_helper_mtc0_count(cpu_env, arg); rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -5148,7 +5166,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 10: switch (sel) { case 0: - gen_helper_mtc0_entryhi(arg); + gen_helper_mtc0_entryhi(cpu_env, arg); rn = "EntryHi"; break; default: @@ -5158,7 +5176,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 11: switch (sel) { case 0: - gen_helper_mtc0_compare(arg); + gen_helper_mtc0_compare(cpu_env, arg); rn = "Compare"; break; /* 6,7 are implementation dependent */ @@ -5172,7 +5190,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, switch (sel) { case 0: save_cpu_state(ctx, 1); - gen_helper_mtc0_status(arg); + gen_helper_mtc0_status(cpu_env, arg); /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; @@ -5180,14 +5198,14 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_intctl(arg); + gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_srsctl(arg); + gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSCtl"; @@ -5212,7 +5230,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, if (use_icount) { gen_io_start(); } - gen_helper_mtc0_cause(arg); + gen_helper_mtc0_cause(cpu_env, arg); if (use_icount) { gen_io_end(); } @@ -5242,7 +5260,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_helper_mtc0_ebase(arg); + gen_helper_mtc0_ebase(cpu_env, arg); rn = "EBase"; break; default: @@ -5252,7 +5270,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 16: switch (sel) { case 0: - gen_helper_mtc0_config0(arg); + gen_helper_mtc0_config0(cpu_env, arg); rn = "Config"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -5262,7 +5280,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, rn = "Config1"; break; case 2: - gen_helper_mtc0_config2(arg); + gen_helper_mtc0_config2(cpu_env, arg); rn = "Config2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -5280,7 +5298,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 17: switch (sel) { case 0: - gen_helper_mtc0_lladdr(arg); + gen_helper_mtc0_lladdr(cpu_env, arg); rn = "LLAddr"; break; default: @@ -5290,7 +5308,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 18: switch (sel) { case 0 ... 7: - gen_helper_1i(mtc0_watchlo, arg, sel); + gen_helper_0e1i(mtc0_watchlo, arg, sel); rn = "WatchLo"; break; default: @@ -5300,7 +5318,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 19: switch (sel) { case 0 ... 7: - gen_helper_1i(mtc0_watchhi, arg, sel); + gen_helper_0e1i(mtc0_watchhi, arg, sel); rn = "WatchHi"; break; default: @@ -5311,7 +5329,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, switch (sel) { case 0: check_insn(env, ctx, ISA_MIPS3); - gen_helper_mtc0_xcontext(arg); + gen_helper_mtc0_xcontext(cpu_env, arg); rn = "XContext"; break; default: @@ -5322,7 +5340,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, /* Officially reserved, but sel 0 is used for R1x000 framemask */ switch (sel) { case 0: - gen_helper_mtc0_framemask(arg); + gen_helper_mtc0_framemask(cpu_env, arg); rn = "Framemask"; break; default: @@ -5336,32 +5354,32 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 23: switch (sel) { case 0: - gen_helper_mtc0_debug(arg); /* EJTAG support */ + gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; rn = "Debug"; break; case 1: -// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ +// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceControl"; // break; case 2: -// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ +// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceControl2"; // break; case 3: -// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ +// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "UserTraceData"; // break; case 4: -// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ +// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceBPC"; @@ -5384,35 +5402,35 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 25: switch (sel) { case 0: - gen_helper_mtc0_performance0(arg); + gen_helper_mtc0_performance0(cpu_env, arg); rn = "Performance0"; break; case 1: -// gen_helper_mtc0_performance1(arg); +// gen_helper_mtc0_performance1(cpu_env, arg); rn = "Performance1"; // break; case 2: -// gen_helper_mtc0_performance2(arg); +// gen_helper_mtc0_performance2(cpu_env, arg); rn = "Performance2"; // break; case 3: -// gen_helper_mtc0_performance3(arg); +// gen_helper_mtc0_performance3(cpu_env, arg); rn = "Performance3"; // break; case 4: -// gen_helper_mtc0_performance4(arg); +// gen_helper_mtc0_performance4(cpu_env, arg); rn = "Performance4"; // break; case 5: -// gen_helper_mtc0_performance5(arg); +// gen_helper_mtc0_performance5(cpu_env, arg); rn = "Performance5"; // break; case 6: -// gen_helper_mtc0_performance6(arg); +// gen_helper_mtc0_performance6(cpu_env, arg); rn = "Performance6"; // break; case 7: -// gen_helper_mtc0_performance7(arg); +// gen_helper_mtc0_performance7(cpu_env, arg); rn = "Performance7"; // break; default: @@ -5439,14 +5457,14 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 2: case 4: case 6: - gen_helper_mtc0_taglo(arg); + gen_helper_mtc0_taglo(cpu_env, arg); rn = "TagLo"; break; case 1: case 3: case 5: case 7: - gen_helper_mtc0_datalo(arg); + gen_helper_mtc0_datalo(cpu_env, arg); rn = "DataLo"; break; default: @@ -5459,14 +5477,14 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, case 2: case 4: case 6: - gen_helper_mtc0_taghi(arg); + gen_helper_mtc0_taghi(cpu_env, arg); rn = "TagHi"; break; case 1: case 3: case 5: case 7: - gen_helper_mtc0_datahi(arg); + gen_helper_mtc0_datahi(cpu_env, arg); rn = "DataHi"; break; default: @@ -5533,10 +5551,10 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 1: switch (sel) { case 1: - gen_helper_mftc0_vpecontrol(t0); + gen_helper_mftc0_vpecontrol(t0, cpu_env); break; case 2: - gen_helper_mftc0_vpeconf0(t0); + gen_helper_mftc0_vpeconf0(t0, cpu_env); break; default: goto die; @@ -5546,25 +5564,25 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 2: switch (sel) { case 1: - gen_helper_mftc0_tcstatus(t0); + gen_helper_mftc0_tcstatus(t0, cpu_env); break; case 2: - gen_helper_mftc0_tcbind(t0); + gen_helper_mftc0_tcbind(t0, cpu_env); break; case 3: - gen_helper_mftc0_tcrestart(t0); + gen_helper_mftc0_tcrestart(t0, cpu_env); break; case 4: - gen_helper_mftc0_tchalt(t0); + gen_helper_mftc0_tchalt(t0, cpu_env); break; case 5: - gen_helper_mftc0_tccontext(t0); + gen_helper_mftc0_tccontext(t0, cpu_env); break; case 6: - gen_helper_mftc0_tcschedule(t0); + gen_helper_mftc0_tcschedule(t0, cpu_env); break; case 7: - gen_helper_mftc0_tcschefback(t0); + gen_helper_mftc0_tcschefback(t0, cpu_env); break; default: gen_mfc0(env, ctx, t0, rt, sel); @@ -5574,7 +5592,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 10: switch (sel) { case 0: - gen_helper_mftc0_entryhi(t0); + gen_helper_mftc0_entryhi(t0, cpu_env); break; default: gen_mfc0(env, ctx, t0, rt, sel); @@ -5583,7 +5601,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 12: switch (sel) { case 0: - gen_helper_mftc0_status(t0); + gen_helper_mftc0_status(t0, cpu_env); break; default: gen_mfc0(env, ctx, t0, rt, sel); @@ -5592,7 +5610,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 13: switch (sel) { case 0: - gen_helper_mftc0_cause(t0); + gen_helper_mftc0_cause(t0, cpu_env); break; default: goto die; @@ -5602,7 +5620,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 14: switch (sel) { case 0: - gen_helper_mftc0_epc(t0); + gen_helper_mftc0_epc(t0, cpu_env); break; default: goto die; @@ -5612,7 +5630,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 15: switch (sel) { case 1: - gen_helper_mftc0_ebase(t0); + gen_helper_mftc0_ebase(t0, cpu_env); break; default: goto die; @@ -5622,7 +5640,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 16: switch (sel) { case 0 ... 7: - gen_helper_mftc0_configx(t0, tcg_const_tl(sel)); + gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel)); break; default: goto die; @@ -5632,7 +5650,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 23: switch (sel) { case 0: - gen_helper_mftc0_debug(t0); + gen_helper_mftc0_debug(t0, cpu_env); break; default: gen_mfc0(env, ctx, t0, rt, sel); @@ -5645,49 +5663,49 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, } else switch (sel) { /* GPR registers. */ case 0: - gen_helper_1i(mftgpr, t0, rt); + gen_helper_1e0i(mftgpr, t0, rt); break; /* Auxiliary CPU registers */ case 1: switch (rt) { case 0: - gen_helper_1i(mftlo, t0, 0); + gen_helper_1e0i(mftlo, t0, 0); break; case 1: - gen_helper_1i(mfthi, t0, 0); + gen_helper_1e0i(mfthi, t0, 0); break; case 2: - gen_helper_1i(mftacx, t0, 0); + gen_helper_1e0i(mftacx, t0, 0); break; case 4: - gen_helper_1i(mftlo, t0, 1); + gen_helper_1e0i(mftlo, t0, 1); break; case 5: - gen_helper_1i(mfthi, t0, 1); + gen_helper_1e0i(mfthi, t0, 1); break; case 6: - gen_helper_1i(mftacx, t0, 1); + gen_helper_1e0i(mftacx, t0, 1); break; case 8: - gen_helper_1i(mftlo, t0, 2); + gen_helper_1e0i(mftlo, t0, 2); break; case 9: - gen_helper_1i(mfthi, t0, 2); + gen_helper_1e0i(mfthi, t0, 2); break; case 10: - gen_helper_1i(mftacx, t0, 2); + gen_helper_1e0i(mftacx, t0, 2); break; case 12: - gen_helper_1i(mftlo, t0, 3); + gen_helper_1e0i(mftlo, t0, 3); break; case 13: - gen_helper_1i(mfthi, t0, 3); + gen_helper_1e0i(mfthi, t0, 3); break; case 14: - gen_helper_1i(mftacx, t0, 3); + gen_helper_1e0i(mftacx, t0, 3); break; case 16: - gen_helper_mftdsp(t0); + gen_helper_mftdsp(t0, cpu_env); break; default: goto die; @@ -5712,7 +5730,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, break; case 3: /* XXX: For now we support only a single FPU context. */ - gen_helper_1i(cfc1, t0, rt); + gen_helper_1e0i(cfc1, t0, rt); break; /* COP2: Not implemented. */ case 4: @@ -5751,10 +5769,10 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, case 1: switch (sel) { case 1: - gen_helper_mttc0_vpecontrol(t0); + gen_helper_mttc0_vpecontrol(cpu_env, t0); break; case 2: - gen_helper_mttc0_vpeconf0(t0); + gen_helper_mttc0_vpeconf0(cpu_env, t0); break; default: goto die; @@ -5764,25 +5782,25 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, case 2: switch (sel) { case 1: - gen_helper_mttc0_tcstatus(t0); + gen_helper_mttc0_tcstatus(cpu_env, t0); break; case 2: - gen_helper_mttc0_tcbind(t0); + gen_helper_mttc0_tcbind(cpu_env, t0); break; case 3: - gen_helper_mttc0_tcrestart(t0); + gen_helper_mttc0_tcrestart(cpu_env, t0); break; case 4: - gen_helper_mttc0_tchalt(t0); + gen_helper_mttc0_tchalt(cpu_env, t0); break; case 5: - gen_helper_mttc0_tccontext(t0); + gen_helper_mttc0_tccontext(cpu_env, t0); break; case 6: - gen_helper_mttc0_tcschedule(t0); + gen_helper_mttc0_tcschedule(cpu_env, t0); break; case 7: - gen_helper_mttc0_tcschefback(t0); + gen_helper_mttc0_tcschefback(cpu_env, t0); break; default: gen_mtc0(env, ctx, t0, rd, sel); @@ -5792,7 +5810,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, case 10: switch (sel) { case 0: - gen_helper_mttc0_entryhi(t0); + gen_helper_mttc0_entryhi(cpu_env, t0); break; default: gen_mtc0(env, ctx, t0, rd, sel); @@ -5801,7 +5819,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, case 12: switch (sel) { case 0: - gen_helper_mttc0_status(t0); + gen_helper_mttc0_status(cpu_env, t0); break; default: gen_mtc0(env, ctx, t0, rd, sel); @@ -5810,7 +5828,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, case 13: switch (sel) { case 0: - gen_helper_mttc0_cause(t0); + gen_helper_mttc0_cause(cpu_env, t0); break; default: goto die; @@ -5820,7 +5838,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, case 15: switch (sel) { case 1: - gen_helper_mttc0_ebase(t0); + gen_helper_mttc0_ebase(cpu_env, t0); break; default: goto die; @@ -5830,7 +5848,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, case 23: switch (sel) { case 0: - gen_helper_mttc0_debug(t0); + gen_helper_mttc0_debug(cpu_env, t0); break; default: gen_mtc0(env, ctx, t0, rd, sel); @@ -5843,49 +5861,49 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, } else switch (sel) { /* GPR registers. */ case 0: - gen_helper_1i(mttgpr, t0, rd); + gen_helper_0e1i(mttgpr, t0, rd); break; /* Auxiliary CPU registers */ case 1: switch (rd) { case 0: - gen_helper_1i(mttlo, t0, 0); + gen_helper_0e1i(mttlo, t0, 0); break; case 1: - gen_helper_1i(mtthi, t0, 0); + gen_helper_0e1i(mtthi, t0, 0); break; case 2: - gen_helper_1i(mttacx, t0, 0); + gen_helper_0e1i(mttacx, t0, 0); break; case 4: - gen_helper_1i(mttlo, t0, 1); + gen_helper_0e1i(mttlo, t0, 1); break; case 5: - gen_helper_1i(mtthi, t0, 1); + gen_helper_0e1i(mtthi, t0, 1); break; case 6: - gen_helper_1i(mttacx, t0, 1); + gen_helper_0e1i(mttacx, t0, 1); break; case 8: - gen_helper_1i(mttlo, t0, 2); + gen_helper_0e1i(mttlo, t0, 2); break; case 9: - gen_helper_1i(mtthi, t0, 2); + gen_helper_0e1i(mtthi, t0, 2); break; case 10: - gen_helper_1i(mttacx, t0, 2); + gen_helper_0e1i(mttacx, t0, 2); break; case 12: - gen_helper_1i(mttlo, t0, 3); + gen_helper_0e1i(mttlo, t0, 3); break; case 13: - gen_helper_1i(mtthi, t0, 3); + gen_helper_0e1i(mtthi, t0, 3); break; case 14: - gen_helper_1i(mttacx, t0, 3); + gen_helper_0e1i(mttacx, t0, 3); break; case 16: - gen_helper_mttdsp(t0); + gen_helper_mttdsp(cpu_env, t0); break; default: goto die; @@ -5910,7 +5928,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, break; case 3: /* XXX: For now we support only a single FPU context. */ - gen_helper_1i(ctc1, t0, rd); + gen_helper_0e1i(ctc1, t0, rd); break; /* COP2: Not implemented. */ case 4: @@ -5995,30 +6013,30 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, opn = "tlbwi"; if (!env->tlb->helper_tlbwi) goto die; - gen_helper_tlbwi(); + gen_helper_tlbwi(cpu_env); break; case OPC_TLBWR: opn = "tlbwr"; if (!env->tlb->helper_tlbwr) goto die; - gen_helper_tlbwr(); + gen_helper_tlbwr(cpu_env); break; case OPC_TLBP: opn = "tlbp"; if (!env->tlb->helper_tlbp) goto die; - gen_helper_tlbp(); + gen_helper_tlbp(cpu_env); break; case OPC_TLBR: opn = "tlbr"; if (!env->tlb->helper_tlbr) goto die; - gen_helper_tlbr(); + gen_helper_tlbr(cpu_env); break; case OPC_ERET: opn = "eret"; check_insn(env, ctx, ISA_MIPS2); - gen_helper_eret(); + gen_helper_eret(cpu_env); ctx->bstate = BS_EXCP; break; case OPC_DERET: @@ -6028,7 +6046,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, MIPS_INVAL(opn); generate_exception(ctx, EXCP_RI); } else { - gen_helper_deret(); + gen_helper_deret(cpu_env); ctx->bstate = BS_EXCP; } break; @@ -6039,7 +6057,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, ctx->pc += 4; save_cpu_state(ctx, 1); ctx->pc -= 4; - gen_helper_wait(); + gen_helper_wait(cpu_env); ctx->bstate = BS_EXCP; break; default: @@ -6340,13 +6358,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) opn = "mtc1"; break; case OPC_CFC1: - gen_helper_1i(cfc1, t0, fs); + gen_helper_1e0i(cfc1, t0, fs); gen_store_gpr(t0, rt); opn = "cfc1"; break; case OPC_CTC1: gen_load_gpr(t0, rt); - gen_helper_1i(ctc1, t0, fs); + gen_helper_0e1i(ctc1, t0, fs); opn = "ctc1"; break; #if defined(TARGET_MIPS64) @@ -6543,7 +6561,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); - gen_helper_float_add_s(fp0, fp0, fp1); + gen_helper_float_add_s(fp0, cpu_env, fp0, fp1); tcg_temp_free_i32(fp1); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); @@ -6558,7 +6576,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); - gen_helper_float_sub_s(fp0, fp0, fp1); + gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1); tcg_temp_free_i32(fp1); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); @@ -6573,7 +6591,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); - gen_helper_float_mul_s(fp0, fp0, fp1); + gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1); tcg_temp_free_i32(fp1); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); @@ -6588,7 +6606,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); - gen_helper_float_div_s(fp0, fp0, fp1); + gen_helper_float_div_s(fp0, cpu_env, fp0, fp1); tcg_temp_free_i32(fp1); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); @@ -6601,7 +6619,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_sqrt_s(fp0, fp0); + gen_helper_float_sqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6646,7 +6664,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr32(fp32, fs); - gen_helper_float_roundl_s(fp64, fp32); + gen_helper_float_roundl_s(fp64, cpu_env, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); @@ -6660,7 +6678,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr32(fp32, fs); - gen_helper_float_truncl_s(fp64, fp32); + gen_helper_float_truncl_s(fp64, cpu_env, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); @@ -6674,7 +6692,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr32(fp32, fs); - gen_helper_float_ceill_s(fp64, fp32); + gen_helper_float_ceill_s(fp64, cpu_env, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); @@ -6688,7 +6706,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr32(fp32, fs); - gen_helper_float_floorl_s(fp64, fp32); + gen_helper_float_floorl_s(fp64, cpu_env, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); @@ -6700,7 +6718,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_roundw_s(fp0, fp0); + gen_helper_float_roundw_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6711,7 +6729,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_truncw_s(fp0, fp0); + gen_helper_float_truncw_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6722,7 +6740,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_ceilw_s(fp0, fp0); + gen_helper_float_ceilw_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6733,7 +6751,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_floorw_s(fp0, fp0); + gen_helper_float_floorw_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6781,7 +6799,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_recip_s(fp0, fp0); + gen_helper_float_recip_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6793,7 +6811,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_rsqrt_s(fp0, fp0); + gen_helper_float_rsqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6807,7 +6825,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); - gen_helper_float_recip2_s(fp0, fp0, fp1); + gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1); tcg_temp_free_i32(fp1); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); @@ -6820,7 +6838,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_recip1_s(fp0, fp0); + gen_helper_float_recip1_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6832,7 +6850,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_rsqrt1_s(fp0, fp0); + gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6846,7 +6864,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); - gen_helper_float_rsqrt2_s(fp0, fp0, fp1); + gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1); tcg_temp_free_i32(fp1); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); @@ -6860,7 +6878,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr32(fp32, fs); - gen_helper_float_cvtd_s(fp64, fp32); + gen_helper_float_cvtd_s(fp64, cpu_env, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); @@ -6872,7 +6890,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_cvtw_s(fp0, fp0); + gen_helper_float_cvtw_s(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -6885,7 +6903,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr32(fp32, fs); - gen_helper_float_cvtl_s(fp64, fp32); + gen_helper_float_cvtl_s(fp64, cpu_env, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); @@ -6941,7 +6959,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_add_d(fp0, fp0, fp1); + gen_helper_float_add_d(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -6957,7 +6975,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_sub_d(fp0, fp0, fp1); + gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -6973,7 +6991,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_mul_d(fp0, fp0, fp1); + gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -6989,7 +7007,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_div_d(fp0, fp0, fp1); + gen_helper_float_div_d(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7003,7 +7021,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_sqrt_d(fp0, fp0); + gen_helper_float_sqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7050,7 +7068,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_roundl_d(fp0, fp0); + gen_helper_float_roundl_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7062,7 +7080,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_truncl_d(fp0, fp0); + gen_helper_float_truncl_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7074,7 +7092,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_ceill_d(fp0, fp0); + gen_helper_float_ceill_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7086,7 +7104,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_floorl_d(fp0, fp0); + gen_helper_float_floorl_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7099,7 +7117,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_roundw_d(fp32, fp64); + gen_helper_float_roundw_d(fp32, cpu_env, fp64); tcg_temp_free_i64(fp64); gen_store_fpr32(fp32, fd); tcg_temp_free_i32(fp32); @@ -7113,7 +7131,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_truncw_d(fp32, fp64); + gen_helper_float_truncw_d(fp32, cpu_env, fp64); tcg_temp_free_i64(fp64); gen_store_fpr32(fp32, fd); tcg_temp_free_i32(fp32); @@ -7127,7 +7145,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_ceilw_d(fp32, fp64); + gen_helper_float_ceilw_d(fp32, cpu_env, fp64); tcg_temp_free_i64(fp64); gen_store_fpr32(fp32, fd); tcg_temp_free_i32(fp32); @@ -7141,7 +7159,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_floorw_d(fp32, fp64); + gen_helper_float_floorw_d(fp32, cpu_env, fp64); tcg_temp_free_i64(fp64); gen_store_fpr32(fp32, fd); tcg_temp_free_i32(fp32); @@ -7190,7 +7208,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_recip_d(fp0, fp0); + gen_helper_float_recip_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7202,7 +7220,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_rsqrt_d(fp0, fp0); + gen_helper_float_rsqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7216,7 +7234,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_recip2_d(fp0, fp0, fp1); + gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7229,7 +7247,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_recip1_d(fp0, fp0); + gen_helper_float_recip1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7241,7 +7259,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_rsqrt1_d(fp0, fp0); + gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7255,7 +7273,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_rsqrt2_d(fp0, fp0, fp1); + gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7293,7 +7311,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_cvts_d(fp32, fp64); + gen_helper_float_cvts_d(fp32, cpu_env, fp64); tcg_temp_free_i64(fp64); gen_store_fpr32(fp32, fd); tcg_temp_free_i32(fp32); @@ -7307,7 +7325,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_cvtw_d(fp32, fp64); + gen_helper_float_cvtw_d(fp32, cpu_env, fp64); tcg_temp_free_i64(fp64); gen_store_fpr32(fp32, fd); tcg_temp_free_i32(fp32); @@ -7320,7 +7338,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_cvtl_d(fp0, fp0); + gen_helper_float_cvtl_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7331,7 +7349,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_cvts_w(fp0, fp0); + gen_helper_float_cvts_w(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -7344,7 +7362,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr32(fp32, fs); - gen_helper_float_cvtd_w(fp64, fp32); + gen_helper_float_cvtd_w(fp64, cpu_env, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); @@ -7358,7 +7376,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp64 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_cvts_l(fp32, fp64); + gen_helper_float_cvts_l(fp32, cpu_env, fp64); tcg_temp_free_i64(fp64); gen_store_fpr32(fp32, fd); tcg_temp_free_i32(fp32); @@ -7371,7 +7389,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_cvtd_l(fp0, fp0); + gen_helper_float_cvtd_l(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7383,7 +7401,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_cvtps_pw(fp0, fp0); + gen_helper_float_cvtps_pw(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7397,7 +7415,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_add_ps(fp0, fp0, fp1); + gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7412,7 +7430,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_sub_ps(fp0, fp0, fp1); + gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7427,7 +7445,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_mul_ps(fp0, fp0, fp1); + gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7515,7 +7533,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); - gen_helper_float_addr_ps(fp0, fp0, fp1); + gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7530,7 +7548,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); - gen_helper_float_mulr_ps(fp0, fp0, fp1); + gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7545,7 +7563,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_recip2_ps(fp0, fp0, fp1); + gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7558,7 +7576,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_recip1_ps(fp0, fp0); + gen_helper_float_recip1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7570,7 +7588,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_rsqrt1_ps(fp0, fp0); + gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7584,7 +7602,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_rsqrt2_ps(fp0, fp0, fp1); + gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -7597,7 +7615,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32h(fp0, fs); - gen_helper_float_cvts_pu(fp0, fp0); + gen_helper_float_cvts_pu(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -7609,7 +7627,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_cvtpw_ps(fp0, fp0); + gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } @@ -7621,7 +7639,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(fp0, fs); - gen_helper_float_cvts_pl(fp0, fp0); + gen_helper_float_cvts_pl(fp0, cpu_env, fp0); gen_store_fpr32(fp0, fd); tcg_temp_free_i32(fp0); } @@ -7887,7 +7905,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_muladd_s(fp2, fp0, fp1, fp2); + gen_helper_float_muladd_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -7906,7 +7924,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_muladd_d(fp2, fp0, fp1, fp2); + gen_helper_float_muladd_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -7924,7 +7942,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2); + gen_helper_float_muladd_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -7942,7 +7960,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2); + gen_helper_float_mulsub_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -7961,7 +7979,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2); + gen_helper_float_mulsub_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -7979,7 +7997,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2); + gen_helper_float_mulsub_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -7997,7 +8015,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2); + gen_helper_float_nmuladd_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -8016,7 +8034,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2); + gen_helper_float_nmuladd_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8034,7 +8052,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2); + gen_helper_float_nmuladd_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8052,7 +8070,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2); + gen_helper_float_nmulsub_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -8071,7 +8089,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2); + gen_helper_float_nmulsub_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8089,7 +8107,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2); + gen_helper_float_nmulsub_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8122,22 +8140,22 @@ gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd) switch (rd) { case 0: save_cpu_state(ctx, 1); - gen_helper_rdhwr_cpunum(t0); + gen_helper_rdhwr_cpunum(t0, cpu_env); gen_store_gpr(t0, rt); break; case 1: save_cpu_state(ctx, 1); - gen_helper_rdhwr_synci_step(t0); + gen_helper_rdhwr_synci_step(t0, cpu_env); gen_store_gpr(t0, rt); break; case 2: save_cpu_state(ctx, 1); - gen_helper_rdhwr_cc(t0); + gen_helper_rdhwr_cc(t0, cpu_env); gen_store_gpr(t0, rt); break; case 3: save_cpu_state(ctx, 1); - gen_helper_rdhwr_ccres(t0); + gen_helper_rdhwr_ccres(t0, cpu_env); gen_store_gpr(t0, rt); break; case 29: @@ -8214,7 +8232,7 @@ static void handle_delay_slot (CPUMIPSState *env, DisasContext *ctx, } if (ctx->singlestep_enabled) { save_cpu_state(ctx, 0); - gen_helper_0i(raise_exception, EXCP_DEBUG); + gen_helper_0e0i(raise_exception, EXCP_DEBUG); } tcg_gen_exit_tb(0); break; @@ -8678,7 +8696,7 @@ static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx, static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) { - int extend = lduw_code(ctx->pc + 2); + int extend = cpu_lduw_code(env, ctx->pc + 2); int op, rx, ry, funct, sa; int16_t imm, offset; @@ -8904,7 +8922,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset = lduw_code(ctx->pc + 2); + offset = cpu_lduw_code(env, ctx->pc + 2); offset = (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; @@ -9855,17 +9873,17 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, save_cpu_state(ctx, 1); switch (opc) { case LWM32: - gen_helper_lwm(t0, t1, t2); + gen_helper_lwm(cpu_env, t0, t1, t2); break; case SWM32: - gen_helper_swm(t0, t1, t2); + gen_helper_swm(cpu_env, t0, t1, t2); break; #ifdef TARGET_MIPS64 case LDM: - gen_helper_ldm(t0, t1, t2); + gen_helper_ldm(cpu_env, t0, t1, t2); break; case SDM: - gen_helper_sdm(t0, t1, t2); + gen_helper_sdm(cpu_env, t0, t1, t2); break; #endif } @@ -10287,7 +10305,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, TCGv t0 = tcg_temp_new(); save_cpu_state(ctx, 1); - gen_helper_di(t0); + gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rs); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -10300,7 +10318,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs, TCGv t0 = tcg_temp_new(); save_cpu_state(ctx, 1); - gen_helper_ei(t0); + gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rs); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -10635,7 +10653,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, uint32_t op, minor, mips32_op; uint32_t cond, fmt, cc; - insn = lduw_code(ctx->pc + 2); + insn = cpu_lduw_code(env, ctx->pc + 2); ctx->opcode = (ctx->opcode << 16) | insn; rt = (ctx->opcode >> 21) & 0x1f; @@ -11827,7 +11845,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) MIPS_INVAL("PMON / selsl"); generate_exception(ctx, EXCP_RI); #else - gen_helper_0i(pmon, sa); + gen_helper_0e0i(pmon, sa); #endif break; case OPC_SYSCALL: @@ -12045,7 +12063,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) save_cpu_state(ctx, 1); gen_load_gpr(t0, rs); - gen_helper_yield(t0, t0); + gen_helper_yield(t0, cpu_env, t0); gen_store_gpr(t0, rd); tcg_temp_free(t0); } @@ -12144,18 +12162,18 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_DVPE: check_insn(env, ctx, ASE_MT); - gen_helper_dvpe(t0); + gen_helper_dvpe(t0, cpu_env); gen_store_gpr(t0, rt); break; case OPC_EVPE: check_insn(env, ctx, ASE_MT); - gen_helper_evpe(t0); + gen_helper_evpe(t0, cpu_env); gen_store_gpr(t0, rt); break; case OPC_DI: check_insn(env, ctx, ISA_MIPS32R2); save_cpu_state(ctx, 1); - gen_helper_di(t0); + gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -12163,7 +12181,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_EI: check_insn(env, ctx, ISA_MIPS32R2); save_cpu_state(ctx, 1); - gen_helper_ei(t0); + gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -12432,7 +12450,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, if (bp->pc == ctx.pc) { save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; - gen_helper_0i(raise_exception, EXCP_DEBUG); + gen_helper_0e0i(raise_exception, EXCP_DEBUG); /* Include the breakpoint location or the tb won't * be flushed when it must be. */ ctx.pc += 4; @@ -12458,14 +12476,14 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, is_branch = 0; if (!(ctx.hflags & MIPS_HFLAG_M16)) { - ctx.opcode = ldl_code(ctx.pc); + ctx.opcode = cpu_ldl_code(env, ctx.pc); insn_bytes = 4; decode_opc(env, &ctx, &is_branch); } else if (env->insn_flags & ASE_MICROMIPS) { - ctx.opcode = lduw_code(ctx.pc); + ctx.opcode = cpu_lduw_code(env, ctx.pc); insn_bytes = decode_micromips_opc(env, &ctx, &is_branch); } else if (env->insn_flags & ASE_MIPS16) { - ctx.opcode = lduw_code(ctx.pc); + ctx.opcode = cpu_lduw_code(env, ctx.pc); insn_bytes = decode_mips16_opc(env, &ctx, &is_branch); } else { generate_exception(&ctx, EXCP_RI); @@ -12502,7 +12520,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, gen_io_end(); if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) { save_cpu_state(&ctx, ctx.bstate == BS_NONE); - gen_helper_0i(raise_exception, EXCP_DEBUG); + gen_helper_0e0i(raise_exception, EXCP_DEBUG); } else { switch (ctx.bstate) { case BS_STOP: |