diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/esp.c | 11 | ||||
| -rw-r--r-- | hw/pcnet.c | 11 | ||||
| -rw-r--r-- | hw/sparc32_dma.c | 20 | ||||
| -rw-r--r-- | hw/sun4m.c | 13 |
4 files changed, 34 insertions, 21 deletions
@@ -344,6 +344,12 @@ static void esp_reset(void *opaque) s->do_cmd = 0; } +static void parent_esp_reset(void *opaque, int irq, int level) +{ + if (level) + esp_reset(opaque); +} + static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) { ESPState *s = opaque; @@ -569,7 +575,7 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) } void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, - void *dma_opaque, qemu_irq irq) + void *dma_opaque, qemu_irq irq, qemu_irq *reset) { ESPState *s; int esp_io_memory; @@ -581,7 +587,6 @@ void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, s->bd = bd; s->irq = irq; s->dma_opaque = dma_opaque; - sparc32_dma_set_reset_data(dma_opaque, esp_reset, s); esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s); cpu_register_physical_memory(espaddr, ESP_SIZE, esp_io_memory); @@ -591,5 +596,7 @@ void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr, register_savevm("esp", espaddr, 3, esp_save, esp_load, s); qemu_register_reset(esp_reset, s); + *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1); + return s; } diff --git a/hw/pcnet.c b/hw/pcnet.c index 7f7c2de378..a086e6712a 100644 --- a/hw/pcnet.c +++ b/hw/pcnet.c @@ -2011,6 +2011,12 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn) #if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure +static void parent_lance_reset(void *opaque, int irq, int level) +{ + if (level) + pcnet_h_reset(opaque); +} + static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { @@ -2047,7 +2053,7 @@ static CPUWriteMemoryFunc *lance_mem_write[3] = { }; void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, - qemu_irq irq) + qemu_irq irq, qemu_irq *reset) { PCNetState *d; int lance_io_memory; @@ -2060,7 +2066,8 @@ void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d); d->dma_opaque = dma_opaque; - sparc32_dma_set_reset_data(dma_opaque, pcnet_h_reset, d); + + *reset = *qemu_allocate_irqs(parent_lance_reset, d, 1); cpu_register_physical_memory(leaddr, 4, lance_io_memory); diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index f26b4bec76..1946ce2799 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -58,9 +58,9 @@ typedef struct DMAState DMAState; struct DMAState { uint32_t dmaregs[DMA_REGS]; qemu_irq irq; - void *iommu, *dev_opaque; - void (*dev_reset)(void *dev_opaque); + void *iommu; qemu_irq *pic; + qemu_irq dev_reset; }; /* Note: on sparc, the lance 16 bit bus is swapped */ @@ -178,7 +178,8 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) qemu_irq_lower(s->irq); } if (val & DMA_RESET) { - s->dev_reset(s->dev_opaque); + qemu_irq_raise(s->dev_reset); + qemu_irq_lower(s->dev_reset); } else if (val & DMA_DRAIN_FIFO) { val &= ~DMA_DRAIN_FIFO; } else if (val == 0) @@ -238,7 +239,7 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id) } void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, - void *iommu, qemu_irq **dev_irq) + void *iommu, qemu_irq **dev_irq, qemu_irq **reset) { DMAState *s; int dma_io_memory; @@ -257,14 +258,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, qemu_register_reset(dma_reset, s); *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1); - return s; -} - -void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque), - void *dev_opaque) -{ - DMAState *s = opaque; + *reset = &s->dev_reset; - s->dev_reset = dev_reset; - s->dev_opaque = dev_opaque; + return s; } diff --git a/hw/sun4m.c b/hw/sun4m.c index 5974812670..dba6f38789 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -315,6 +315,7 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, const sparc_def_t *def; qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, *espdma_irq, *ledma_irq; + qemu_irq *esp_reset, *le_reset; /* init CPUs */ sparc_find_by_name(cpu_model, &def); @@ -352,9 +353,11 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, hwdef->clock_irq); espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], - iommu, &espdma_irq); + iommu, &espdma_irq, &esp_reset); + ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, - slavio_irq[hwdef->le_irq], iommu, &ledma_irq); + slavio_irq[hwdef->le_irq], iommu, &ledma_irq, + &le_reset); if (graphic_depth != 8 && graphic_depth != 24) { fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); @@ -365,7 +368,7 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, if (nd_table[0].model == NULL || strcmp(nd_table[0].model, "lance") == 0) { - lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq); + lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); } else if (strcmp(nd_table[0].model, "?") == 0) { fprintf(stderr, "qemu: Supported NICs: lance\n"); exit (1); @@ -389,7 +392,9 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1], serial_hds[0]); fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table); - main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq); + + main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq, + esp_reset); for (i = 0; i < MAX_DISKS; i++) { if (bs_table[i]) { |