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-rw-r--r--hw/misc/Makefile.objs2
-rw-r--r--hw/misc/aspeed_scu.c45
-rw-r--r--hw/misc/aspeed_sdmc.c280
-rw-r--r--hw/misc/edu.c18
-rw-r--r--hw/misc/imx25_ccm.c2
-rw-r--r--hw/misc/imx31_ccm.c2
-rw-r--r--hw/misc/imx6_ccm.c4
-rw-r--r--hw/misc/imx6_src.c2
-rw-r--r--hw/misc/ivshmem.c28
-rw-r--r--hw/misc/macio/macio.c26
-rw-r--r--hw/misc/milkymist-pfpu.c2
11 files changed, 372 insertions, 39 deletions
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 4cfbd1024a..1a89615a62 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -52,4 +52,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_EDU) += edu.o
obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
obj-$(CONFIG_AUX) += auxbus.o
-obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o
+obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index c7e2c8263f..b1f3e6f6b8 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -120,6 +120,41 @@ static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
[BMC_DEV_ID] = 0x00002402U
};
+/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
+/* AST2500 revision A1 */
+
+static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
+ [SYS_RST_CTRL] = 0xFFCFFEDCU,
+ [CLK_SEL] = 0xF3F40000U,
+ [CLK_STOP_CTRL] = 0x19FC3E8BU,
+ [D2PLL_PARAM] = 0x00026108U,
+ [MPLL_PARAM] = 0x00030291U,
+ [HPLL_PARAM] = 0x93000400U,
+ [MISC_CTRL1] = 0x00000010U,
+ [PCI_CTRL1] = 0x20001A03U,
+ [PCI_CTRL2] = 0x20001A03U,
+ [PCI_CTRL3] = 0x04000030U,
+ [SYS_RST_STATUS] = 0x00000001U,
+ [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
+ [MISC_CTRL2] = 0x00000023U,
+ [RNG_CTRL] = 0x0000000EU,
+ [PINMUX_CTRL2] = 0x0000F000U,
+ [PINMUX_CTRL3] = 0x03000000U,
+ [PINMUX_CTRL4] = 0x00000000U,
+ [PINMUX_CTRL5] = 0x0000A000U,
+ [WDT_RST_CTRL] = 0x023FFFF3U,
+ [PINMUX_CTRL8] = 0xFFFF0000U,
+ [PINMUX_CTRL9] = 0x000FFFFFU,
+ [FREE_CNTR4] = 0x000000FFU,
+ [FREE_CNTR4_EXT] = 0x000000FFU,
+ [CPU2_BASE_SEG1] = 0x80000000U,
+ [CPU2_BASE_SEG4] = 0x1E600000U,
+ [CPU2_BASE_SEG5] = 0xC0000000U,
+ [UART_HPLL_CLK] = 0x00001903U,
+ [PCIE_CTRL] = 0x0000007BU,
+ [BMC_DEV_ID] = 0x00002402U
+};
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -198,6 +233,10 @@ static void aspeed_scu_reset(DeviceState *dev)
case AST2400_A0_SILICON_REV:
reset = ast2400_a0_resets;
break;
+ case AST2500_A0_SILICON_REV:
+ case AST2500_A1_SILICON_REV:
+ reset = ast2500_a1_resets;
+ break;
default:
g_assert_not_reached();
}
@@ -208,7 +247,11 @@ static void aspeed_scu_reset(DeviceState *dev)
s->regs[HW_STRAP2] = s->hw_strap2;
}
-static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, };
+static uint32_t aspeed_silicon_revs[] = {
+ AST2400_A0_SILICON_REV,
+ AST2500_A0_SILICON_REV,
+ AST2500_A1_SILICON_REV,
+};
bool is_supported_silicon_rev(uint32_t silicon_rev)
{
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
new file mode 100644
index 0000000000..8830dc084c
--- /dev/null
+++ b/hw/misc/aspeed_sdmc.c
@@ -0,0 +1,280 @@
+/*
+ * ASPEED SDRAM Memory Controller
+ *
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/misc/aspeed_sdmc.h"
+#include "hw/misc/aspeed_scu.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "trace.h"
+
+/* Protection Key Register */
+#define R_PROT (0x00 / 4)
+#define PROT_KEY_UNLOCK 0xFC600309
+
+/* Configuration Register */
+#define R_CONF (0x04 / 4)
+
+/*
+ * Configuration register Ox4 (for Aspeed AST2400 SOC)
+ *
+ * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
+ * what we care about right now as it is checked by U-Boot to
+ * determine the RAM size.
+ */
+
+#define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
+#define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
+#define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
+#define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
+#define ASPEED_SDMC_ECC_ENABLE (1 << 7)
+#define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
+#define ASPEED_SDMC_DRAM_BANK (1 << 5)
+#define ASPEED_SDMC_DRAM_BURST (1 << 4)
+#define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
+#define ASPEED_SDMC_VGA_8MB 0x0
+#define ASPEED_SDMC_VGA_16MB 0x1
+#define ASPEED_SDMC_VGA_32MB 0x2
+#define ASPEED_SDMC_VGA_64MB 0x3
+#define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
+#define ASPEED_SDMC_DRAM_64MB 0x0
+#define ASPEED_SDMC_DRAM_128MB 0x1
+#define ASPEED_SDMC_DRAM_256MB 0x2
+#define ASPEED_SDMC_DRAM_512MB 0x3
+
+#define ASPEED_SDMC_READONLY_MASK \
+ (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
+ ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
+/*
+ * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
+ *
+ * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
+ * should be set to 1 for the AST2500 SOC.
+ */
+#define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
+#define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
+#define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
+#define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
+#define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
+#define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
+#define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
+#define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
+#define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
+
+/* DRAM size definitions differs */
+#define ASPEED_SDMC_AST2500_128MB 0x0
+#define ASPEED_SDMC_AST2500_256MB 0x1
+#define ASPEED_SDMC_AST2500_512MB 0x2
+#define ASPEED_SDMC_AST2500_1024MB 0x3
+
+#define ASPEED_SDMC_AST2500_READONLY_MASK \
+ (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
+ ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
+ ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
+
+static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
+{
+ AspeedSDMCState *s = ASPEED_SDMC(opaque);
+
+ addr >>= 2;
+
+ if (addr >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+ }
+
+ return s->regs[addr];
+}
+
+static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedSDMCState *s = ASPEED_SDMC(opaque);
+
+ addr >>= 2;
+
+ if (addr >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return;
+ }
+
+ if (addr != R_PROT && s->regs[R_PROT] != PROT_KEY_UNLOCK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
+ return;
+ }
+
+ if (addr == R_CONF) {
+ /* Make sure readonly bits are kept */
+ switch (s->silicon_rev) {
+ case AST2400_A0_SILICON_REV:
+ data &= ~ASPEED_SDMC_READONLY_MASK;
+ break;
+ case AST2500_A0_SILICON_REV:
+ data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+
+ s->regs[addr] = data;
+}
+
+static const MemoryRegionOps aspeed_sdmc_ops = {
+ .read = aspeed_sdmc_read,
+ .write = aspeed_sdmc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+};
+
+static int ast2400_rambits(AspeedSDMCState *s)
+{
+ switch (s->ram_size >> 20) {
+ case 64:
+ return ASPEED_SDMC_DRAM_64MB;
+ case 128:
+ return ASPEED_SDMC_DRAM_128MB;
+ case 256:
+ return ASPEED_SDMC_DRAM_256MB;
+ case 512:
+ return ASPEED_SDMC_DRAM_512MB;
+ default:
+ break;
+ }
+
+ /* use a common default */
+ error_report("warning: Invalid RAM size 0x%" PRIx64
+ ". Using default 256M", s->ram_size);
+ s->ram_size = 256 << 20;
+ return ASPEED_SDMC_DRAM_256MB;
+}
+
+static int ast2500_rambits(AspeedSDMCState *s)
+{
+ switch (s->ram_size >> 20) {
+ case 128:
+ return ASPEED_SDMC_AST2500_128MB;
+ case 256:
+ return ASPEED_SDMC_AST2500_256MB;
+ case 512:
+ return ASPEED_SDMC_AST2500_512MB;
+ case 1024:
+ return ASPEED_SDMC_AST2500_1024MB;
+ default:
+ break;
+ }
+
+ /* use a common default */
+ error_report("warning: Invalid RAM size 0x%" PRIx64
+ ". Using default 512M", s->ram_size);
+ s->ram_size = 512 << 20;
+ return ASPEED_SDMC_AST2500_512MB;
+}
+
+static void aspeed_sdmc_reset(DeviceState *dev)
+{
+ AspeedSDMCState *s = ASPEED_SDMC(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ /* Set ram size bit and defaults values */
+ switch (s->silicon_rev) {
+ case AST2400_A0_SILICON_REV:
+ s->regs[R_CONF] |=
+ ASPEED_SDMC_VGA_COMPAT |
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
+ break;
+
+ case AST2500_A0_SILICON_REV:
+ case AST2500_A1_SILICON_REV:
+ s->regs[R_CONF] |=
+ ASPEED_SDMC_HW_VERSION(1) |
+ ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ AspeedSDMCState *s = ASPEED_SDMC(dev);
+
+ if (!is_supported_silicon_rev(s->silicon_rev)) {
+ error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
+ s->silicon_rev);
+ return;
+ }
+
+ switch (s->silicon_rev) {
+ case AST2400_A0_SILICON_REV:
+ s->ram_bits = ast2400_rambits(s);
+ break;
+ case AST2500_A0_SILICON_REV:
+ case AST2500_A1_SILICON_REV:
+ s->ram_bits = ast2500_rambits(s);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
+ TYPE_ASPEED_SDMC, 0x1000);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_aspeed_sdmc = {
+ .name = "aspeed.sdmc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property aspeed_sdmc_properties[] = {
+ DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
+ DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = aspeed_sdmc_realize;
+ dc->reset = aspeed_sdmc_reset;
+ dc->desc = "ASPEED SDRAM Memory Controller";
+ dc->vmsd = &vmstate_aspeed_sdmc;
+ dc->props = aspeed_sdmc_properties;
+}
+
+static const TypeInfo aspeed_sdmc_info = {
+ .name = TYPE_ASPEED_SDMC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedSDMCState),
+ .class_init = aspeed_sdmc_class_init,
+};
+
+static void aspeed_sdmc_register_types(void)
+{
+ type_register_static(&aspeed_sdmc_info);
+}
+
+type_init(aspeed_sdmc_register_types);
diff --git a/hw/misc/edu.c b/hw/misc/edu.c
index 888ba49a0e..401039c100 100644
--- a/hw/misc/edu.c
+++ b/hw/misc/edu.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
+#include "hw/pci/msi.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h" /* iothread mutex */
#include "qapi/visitor.h"
@@ -69,11 +70,20 @@ typedef struct {
uint64_t dma_mask;
} EduState;
+static bool edu_msi_enabled(EduState *edu)
+{
+ return msi_enabled(&edu->pdev);
+}
+
static void edu_raise_irq(EduState *edu, uint32_t val)
{
edu->irq_status |= val;
if (edu->irq_status) {
- pci_set_irq(&edu->pdev, 1);
+ if (edu_msi_enabled(edu)) {
+ msi_notify(&edu->pdev, 0);
+ } else {
+ pci_set_irq(&edu->pdev, 1);
+ }
}
}
@@ -81,7 +91,7 @@ static void edu_lower_irq(EduState *edu, uint32_t val)
{
edu->irq_status &= ~val;
- if (!edu->irq_status) {
+ if (!edu->irq_status && !edu_msi_enabled(edu)) {
pci_set_irq(&edu->pdev, 0);
}
}
@@ -342,6 +352,10 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp)
pci_config_set_interrupt_pin(pci_conf, 1);
+ if (msi_init(pdev, 0, 1, true, false, errp)) {
+ return;
+ }
+
memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
"edu-mmio", 1 << 20);
pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c
index 5cd8c0a9a7..19e948a52d 100644
--- a/hw/misc/imx25_ccm.c
+++ b/hw/misc/imx25_ccm.c
@@ -27,7 +27,7 @@
} \
} while (0)
-static char const *imx25_ccm_reg_name(uint32_t reg)
+static const char *imx25_ccm_reg_name(uint32_t reg)
{
static char unknown[20];
diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c
index 1c03e52c40..b890c383be 100644
--- a/hw/misc/imx31_ccm.c
+++ b/hw/misc/imx31_ccm.c
@@ -29,7 +29,7 @@
} \
} while (0)
-static char const *imx31_ccm_reg_name(uint32_t reg)
+static const char *imx31_ccm_reg_name(uint32_t reg)
{
static char unknown[20];
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
index 17e15d4c92..1b421013a3 100644
--- a/hw/misc/imx6_ccm.c
+++ b/hw/misc/imx6_ccm.c
@@ -26,7 +26,7 @@
} \
} while (0)
-static char const *imx6_ccm_reg_name(uint32_t reg)
+static const char *imx6_ccm_reg_name(uint32_t reg)
{
static char unknown[20];
@@ -99,7 +99,7 @@ static char const *imx6_ccm_reg_name(uint32_t reg)
}
}
-static char const *imx6_analog_reg_name(uint32_t reg)
+static const char *imx6_analog_reg_name(uint32_t reg)
{
static char unknown[20];
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
index 8bb6829575..55b817b8d7 100644
--- a/hw/misc/imx6_src.c
+++ b/hw/misc/imx6_src.c
@@ -27,7 +27,7 @@
} \
} while (0)
-static char const *imx6_src_reg_name(uint32_t reg)
+static const char *imx6_src_reg_name(uint32_t reg)
{
static char unknown[20];
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 40a2ebca20..abeaf3da08 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -88,7 +88,7 @@ typedef struct IVShmemState {
/* exactly one of these two may be set */
HostMemoryBackend *hostmem; /* with interrupts */
- CharDriverState *server_chr; /* without interrupts */
+ CharBackend server_chr; /* without interrupts */
/* registers */
uint32_t intrmask;
@@ -627,8 +627,7 @@ static void ivshmem_read(void *opaque, const uint8_t *buf, int size)
msg = le64_to_cpu(s->msg_buf);
s->msg_buffered_bytes = 0;
- fd = qemu_chr_fe_get_msgfd(s->server_chr);
- IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd);
+ fd = qemu_chr_fe_get_msgfd(&s->server_chr);
process_msg(s, msg, fd, &err);
if (err) {
@@ -643,8 +642,8 @@ static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp)
n = 0;
do {
- ret = qemu_chr_fe_read_all(s->server_chr, (uint8_t *)&msg + n,
- sizeof(msg) - n);
+ ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n,
+ sizeof(msg) - n);
if (ret < 0 && ret != -EINTR) {
error_setg_errno(errp, -ret, "read from server failed");
return INT64_MIN;
@@ -652,7 +651,7 @@ static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp)
n += ret;
} while (n < sizeof(msg));
- *pfd = qemu_chr_fe_get_msgfd(s->server_chr);
+ *pfd = qemu_chr_fe_get_msgfd(&s->server_chr);
return msg;
}
@@ -859,7 +858,7 @@ static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->ivshmem_mmio);
- if (!s->not_legacy_32bit) {
+ if (s->not_legacy_32bit) {
attr |= PCI_BASE_ADDRESS_MEM_TYPE_64;
}
@@ -869,10 +868,11 @@ static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem,
&error_abort);
} else {
- assert(s->server_chr);
+ CharDriverState *chr = qemu_chr_fe_get_driver(&s->server_chr);
+ assert(chr);
IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n",
- s->server_chr->filename);
+ chr->filename);
/* we allocate enough space for 16 peers and grow as needed */
resize_peers(s, 16);
@@ -894,8 +894,8 @@ static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
return;
}
- qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive,
- ivshmem_read, NULL, s);
+ qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive,
+ ivshmem_read, NULL, s, NULL, true);
if (ivshmem_setup_interrupts(s) < 0) {
error_setg(errp, "failed to initialize interrupts");
@@ -1045,6 +1045,7 @@ static void ivshmem_plain_init(Object *obj)
ivshmem_check_memdev_is_busy,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
+ s->not_legacy_32bit = 1;
}
static void ivshmem_plain_realize(PCIDevice *dev, Error **errp)
@@ -1116,13 +1117,14 @@ static void ivshmem_doorbell_init(Object *obj)
s->features |= (1 << IVSHMEM_MSI);
s->legacy_size = SIZE_MAX; /* whatever the server sends */
+ s->not_legacy_32bit = 1;
}
static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp)
{
IVShmemState *s = IVSHMEM_COMMON(dev);
- if (!s->server_chr) {
+ if (!qemu_chr_fe_get_driver(&s->server_chr)) {
error_setg(errp, "You must specify a 'chardev'");
return;
}
@@ -1251,7 +1253,7 @@ static void ivshmem_realize(PCIDevice *dev, Error **errp)
" or ivshmem-doorbell instead");
}
- if (!!s->server_chr + !!s->shmobj != 1) {
+ if (!!qemu_chr_fe_get_driver(&s->server_chr) + !!s->shmobj != 1) {
error_setg(errp, "You must specify either 'shm' or 'chardev'");
return;
}
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index be03926b96..5d57f45dc6 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -89,22 +89,16 @@ static void macio_escc_legacy_setup(MacIOState *macio_state)
MemoryRegion *bar = &macio_state->bar;
int i;
static const int maps[] = {
- 0x00, 0x00,
- 0x02, 0x20,
- 0x04, 0x10,
- 0x06, 0x30,
- 0x08, 0x40,
- 0x0A, 0x50,
- 0x60, 0x60,
- 0x70, 0x70,
- 0x80, 0x70,
- 0x90, 0x80,
- 0xA0, 0x90,
- 0xB0, 0xA0,
- 0xC0, 0xB0,
- 0xD0, 0xC0,
- 0xE0, 0xD0,
- 0xF0, 0xE0,
+ 0x00, 0x00, /* Command B */
+ 0x02, 0x20, /* Command A */
+ 0x04, 0x10, /* Data B */
+ 0x06, 0x30, /* Data A */
+ 0x08, 0x40, /* Enhancement B */
+ 0x0A, 0x50, /* Enhancement A */
+ 0x80, 0x80, /* Recovery count */
+ 0x90, 0x90, /* Start A */
+ 0xa0, 0xa0, /* Start B */
+ 0xb0, 0xb0, /* Detect AB */
};
memory_region_init(escc_legacy, OBJECT(macio_state), "escc-legacy", 256);
diff --git a/hw/misc/milkymist-pfpu.c b/hw/misc/milkymist-pfpu.c
index 1da21a643e..3ca25894f1 100644
--- a/hw/misc/milkymist-pfpu.c
+++ b/hw/misc/milkymist-pfpu.c
@@ -137,7 +137,7 @@ struct MilkymistPFPUState {
};
typedef struct MilkymistPFPUState MilkymistPFPUState;
-static inline hwaddr
+static inline uint32_t
get_dma_address(uint32_t base, uint32_t x, uint32_t y)
{
return base + 8 * (128 * y + x);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 15:34:29 +0000