diff options
Diffstat (limited to 'hw/ide')
| -rw-r--r-- | hw/ide/macio.c | 12 | ||||
| -rw-r--r-- | hw/ide/mmio.c | 10 |
2 files changed, 11 insertions, 11 deletions
diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 692023d42d..a11223e6f0 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -178,7 +178,7 @@ static void pmac_ide_flush(DBDMA_io *io) /* PowerMac IDE memory IO */ static void pmac_ide_writeb (void *opaque, - a_target_phys_addr addr, uint32_t val) + target_phys_addr_t addr, uint32_t val) { MACIOIDEState *d = opaque; @@ -196,7 +196,7 @@ static void pmac_ide_writeb (void *opaque, } } -static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr) +static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr) { uint8_t retval; MACIOIDEState *d = opaque; @@ -218,7 +218,7 @@ static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr) } static void pmac_ide_writew (void *opaque, - a_target_phys_addr addr, uint32_t val) + target_phys_addr_t addr, uint32_t val) { MACIOIDEState *d = opaque; @@ -231,7 +231,7 @@ static void pmac_ide_writew (void *opaque, } } -static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr) +static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr) { uint16_t retval; MACIOIDEState *d = opaque; @@ -249,7 +249,7 @@ static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr) } static void pmac_ide_writel (void *opaque, - a_target_phys_addr addr, uint32_t val) + target_phys_addr_t addr, uint32_t val) { MACIOIDEState *d = opaque; @@ -262,7 +262,7 @@ static void pmac_ide_writel (void *opaque, } } -static uint32_t pmac_ide_readl (void *opaque,a_target_phys_addr addr) +static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr) { uint32_t retval; MACIOIDEState *d = opaque; diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c index a1a7606299..acaa900c89 100644 --- a/hw/ide/mmio.c +++ b/hw/ide/mmio.c @@ -41,7 +41,7 @@ typedef struct { int shift; } MMIOState; -static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr) +static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) { MMIOState *s = (MMIOState*)opaque; IDEBus *bus = s->bus; @@ -52,7 +52,7 @@ static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr) return ide_data_readw(bus, 0); } -static void mmio_ide_write (void *opaque, a_target_phys_addr addr, +static void mmio_ide_write (void *opaque, target_phys_addr_t addr, uint32_t val) { MMIOState *s = (MMIOState*)opaque; @@ -76,14 +76,14 @@ static CPUWriteMemoryFunc * const mmio_ide_writes[] = { mmio_ide_write, }; -static uint32_t mmio_ide_status_read (void *opaque, a_target_phys_addr addr) +static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) { MMIOState *s= (MMIOState*)opaque; IDEBus *bus = s->bus; return ide_status_read(bus, 0); } -static void mmio_ide_cmd_write (void *opaque, a_target_phys_addr addr, +static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, uint32_t val) { MMIOState *s = (MMIOState*)opaque; @@ -122,7 +122,7 @@ static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id) return 0; } -void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2, +void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, qemu_irq irq, int shift, DriveInfo *hd0, DriveInfo *hd1) { |