diff options
| -rw-r--r-- | hw/ppc.c | 28 | ||||
| -rw-r--r-- | hw/ppc4xx_devs.c | 2 | ||||
| -rw-r--r-- | hw/ppc_prep.c | 7 | ||||
| -rw-r--r-- | osdep.h | 7 | ||||
| -rw-r--r-- | target-alpha/exec.h | 9 | ||||
| -rw-r--r-- | target-alpha/op_helper.c | 20 | ||||
| -rw-r--r-- | target-alpha/translate.c | 90 | ||||
| -rw-r--r-- | target-ppc/cpu.h | 2 | ||||
| -rw-r--r-- | target-ppc/exec.h | 8 | ||||
| -rw-r--r-- | target-ppc/helper.c | 145 | ||||
| -rw-r--r-- | target-ppc/helper_regs.h | 10 | ||||
| -rw-r--r-- | target-ppc/op_helper.c | 80 | ||||
| -rw-r--r-- | target-ppc/translate.c | 318 |
13 files changed, 355 insertions, 371 deletions
@@ -393,8 +393,8 @@ struct ppc_tb_t { void *opaque; }; -static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk, - int64_t tb_offset) +static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, + int64_t tb_offset) { /* TB time in tb periods */ return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset; @@ -411,7 +411,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env) return tb & 0xFFFFFFFF; } -static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env) +static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -427,9 +427,8 @@ uint32_t cpu_ppc_load_tbu (CPUState *env) return _cpu_ppc_load_tbu(env); } -static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk, - int64_t *tb_offsetp, - uint64_t value) +static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, + int64_t *tb_offsetp, uint64_t value) { *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", @@ -447,7 +446,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value) &tb_env->tb_offset, tb | (uint64_t)value); } -static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value) +static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -550,8 +549,7 @@ static void cpu_ppc_tb_start (CPUState *env) } } -static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, - uint64_t next) +static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) { ppc_tb_t *tb_env = env->tb_env; uint32_t decr; @@ -594,14 +592,14 @@ uint64_t cpu_ppc_load_purr (CPUState *env) /* When decrementer expires, * all we need to do is generate or queue a CPU exception */ -static always_inline void cpu_ppc_decr_excp (CPUState *env) +static inline void cpu_ppc_decr_excp(CPUState *env) { /* Raise it */ LOG_TB("raise decrementer exception\n"); ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); } -static always_inline void cpu_ppc_hdecr_excp (CPUState *env) +static inline void cpu_ppc_hdecr_excp(CPUState *env) { /* Raise it */ LOG_TB("raise decrementer exception\n"); @@ -635,8 +633,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, (*raise_excp)(env); } -static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, - uint32_t value, int is_excp) +static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, + uint32_t value, int is_excp) { ppc_tb_t *tb_env = env->tb_env; @@ -654,8 +652,8 @@ static void cpu_ppc_decr_cb (void *opaque) _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); } -static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr, - uint32_t value, int is_excp) +static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, + uint32_t value, int is_excp) { ppc_tb_t *tb_env = env->tb_env; diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 8f8a44c395..9c1f7d8cff 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -377,7 +377,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base, return bcr; } -static always_inline target_phys_addr_t sdram_base (uint32_t bcr) +static inline target_phys_addr_t sdram_base(uint32_t bcr) { return bcr & 0xFF800000; } diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 97190a2b7b..3dae4588dd 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -115,7 +115,7 @@ static void _PPC_intack_write (void *opaque, // printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); } -static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr) +static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) { uint32_t retval = 0; @@ -426,9 +426,8 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) return retval; } -static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl, - target_phys_addr_t - addr) +static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, + target_phys_addr_t addr) { if (sysctrl->contiguous_map == 0) { /* 64 KB contiguous space for IOs */ @@ -48,12 +48,9 @@ #endif #ifndef always_inline -#if (__GNUC__ < 3) || defined(__APPLE__) -#define always_inline inline -#else -#define always_inline __attribute__ (( always_inline )) __inline__ +#if !((__GNUC__ < 3) || defined(__APPLE__)) #ifdef __OPTIMIZE__ -#define inline always_inline +#define inline __attribute__ (( always_inline )) __inline__ #endif #endif #else diff --git a/target-alpha/exec.h b/target-alpha/exec.h index 35d6a16775..3533eb1719 100644 --- a/target-alpha/exec.h +++ b/target-alpha/exec.h @@ -39,20 +39,21 @@ register struct CPUAlphaState *env asm(AREG0); #include "softmmu_exec.h" #endif /* !defined(CONFIG_USER_ONLY) */ -static always_inline void env_to_regs(void) +static inline void env_to_regs(void) { } -static always_inline void regs_to_env(void) +static inline void regs_to_env(void) { } -static always_inline int cpu_has_work(CPUState *env) +static inline int cpu_has_work(CPUState *env) { return (env->interrupt_request & CPU_INTERRUPT_HARD); } -static always_inline int cpu_halted(CPUState *env) { +static inline int cpu_halted(CPUState *env) +{ if (!env->halted) return 0; if (cpu_has_work(env)) { diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 22812ca469..e9d2732dfb 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -200,7 +200,7 @@ uint64_t helper_cttz (uint64_t arg) return ctz64(arg); } -static always_inline uint64_t byte_zap (uint64_t op, uint8_t mskb) +static inline uint64_t byte_zap(uint64_t op, uint8_t mskb) { uint64_t mask; @@ -322,7 +322,7 @@ uint64_t helper_cmpbge (uint64_t op1, uint64_t op2) /* Floating point helpers */ /* F floating (VAX) */ -static always_inline uint64_t float32_to_f (float32 fa) +static inline uint64_t float32_to_f(float32 fa) { uint64_t r, exp, mant, sig; CPU_FloatU a; @@ -355,7 +355,7 @@ static always_inline uint64_t float32_to_f (float32 fa) return r; } -static always_inline float32 f_to_float32 (uint64_t a) +static inline float32 f_to_float32(uint64_t a) { uint32_t exp, mant_sig; CPU_FloatU r; @@ -449,7 +449,7 @@ uint64_t helper_sqrtf (uint64_t t) /* G floating (VAX) */ -static always_inline uint64_t float64_to_g (float64 fa) +static inline uint64_t float64_to_g(float64 fa) { uint64_t r, exp, mant, sig; CPU_DoubleU a; @@ -482,7 +482,7 @@ static always_inline uint64_t float64_to_g (float64 fa) return r; } -static always_inline float64 g_to_float64 (uint64_t a) +static inline float64 g_to_float64(uint64_t a) { uint64_t exp, mant_sig; CPU_DoubleU r; @@ -576,7 +576,7 @@ uint64_t helper_sqrtg (uint64_t a) /* S floating (single) */ -static always_inline uint64_t float32_to_s (float32 fa) +static inline uint64_t float32_to_s(float32 fa) { CPU_FloatU a; uint64_t r; @@ -589,7 +589,7 @@ static always_inline uint64_t float32_to_s (float32 fa) return r; } -static always_inline float32 s_to_float32 (uint64_t a) +static inline float32 s_to_float32(uint64_t a) { CPU_FloatU r; r.l = ((a >> 32) & 0xc0000000) | ((a >> 29) & 0x3fffffff); @@ -660,7 +660,7 @@ uint64_t helper_sqrts (uint64_t a) /* T floating (double) */ -static always_inline float64 t_to_float64 (uint64_t a) +static inline float64 t_to_float64(uint64_t a) { /* Memory format is the same as float64 */ CPU_DoubleU r; @@ -668,7 +668,7 @@ static always_inline float64 t_to_float64 (uint64_t a) return r.d; } -static always_inline uint64_t float64_to_t (float64 fa) +static inline uint64_t float64_to_t(float64 fa) { /* Memory format is the same as float64 */ CPU_DoubleU r; @@ -939,7 +939,7 @@ uint64_t helper_cvtlq (uint64_t a) return (int64_t)((int32_t)((a >> 32) | ((a >> 29) & 0x3FFFFFFF))); } -static always_inline uint64_t __helper_cvtql (uint64_t a, int s, int v) +static inline uint64_t __helper_cvtql(uint64_t a, int s, int v) { uint64_t r; diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 1fc5119cb5..1dd85629b3 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -103,8 +103,7 @@ static void alpha_translate_init(void) done_init = 1; } -static always_inline void gen_excp (DisasContext *ctx, - int exception, int error_code) +static inline void gen_excp(DisasContext *ctx, int exception, int error_code) { TCGv_i32 tmp1, tmp2; @@ -116,12 +115,12 @@ static always_inline void gen_excp (DisasContext *ctx, tcg_temp_free_i32(tmp1); } -static always_inline void gen_invalid (DisasContext *ctx) +static inline void gen_invalid(DisasContext *ctx) { gen_excp(ctx, EXCP_OPCDEC, 0); } -static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags) { TCGv tmp = tcg_temp_new(); TCGv_i32 tmp32 = tcg_temp_new_i32(); @@ -132,7 +131,7 @@ static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) tcg_temp_free(tmp); } -static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags) { TCGv tmp = tcg_temp_new(); tcg_gen_qemu_ld64(tmp, t1, flags); @@ -140,7 +139,7 @@ static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) tcg_temp_free(tmp); } -static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags) { TCGv tmp = tcg_temp_new(); TCGv_i32 tmp32 = tcg_temp_new_i32(); @@ -151,22 +150,23 @@ static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) tcg_temp_free(tmp); } -static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags) { tcg_gen_mov_i64(cpu_lock, t1); tcg_gen_qemu_ld32s(t0, t1, flags); } -static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags) { tcg_gen_mov_i64(cpu_lock, t1); tcg_gen_qemu_ld64(t0, t1, flags); } -static always_inline void gen_load_mem (DisasContext *ctx, - void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), - int ra, int rb, int32_t disp16, - int fp, int clear) +static inline void gen_load_mem(DisasContext *ctx, + void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, + int flags), + int ra, int rb, int32_t disp16, int fp, + int clear) { TCGv addr; @@ -190,7 +190,7 @@ static always_inline void gen_load_mem (DisasContext *ctx, tcg_temp_free(addr); } -static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags) { TCGv_i32 tmp32 = tcg_temp_new_i32(); TCGv tmp = tcg_temp_new(); @@ -201,7 +201,7 @@ static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) tcg_temp_free_i32(tmp32); } -static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags) { TCGv tmp = tcg_temp_new(); gen_helper_g_to_memory(tmp, t0); @@ -209,7 +209,7 @@ static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) tcg_temp_free(tmp); } -static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags) { TCGv_i32 tmp32 = tcg_temp_new_i32(); TCGv tmp = tcg_temp_new(); @@ -220,7 +220,7 @@ static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) tcg_temp_free_i32(tmp32); } -static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags) { int l1, l2; @@ -236,7 +236,7 @@ static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) tcg_gen_movi_i64(cpu_lock, -1); } -static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags) +static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags) { int l1, l2; @@ -252,10 +252,11 @@ static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags) tcg_gen_movi_i64(cpu_lock, -1); } -static always_inline void gen_store_mem (DisasContext *ctx, - void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), - int ra, int rb, int32_t disp16, - int fp, int clear, int local) +static inline void gen_store_mem(DisasContext *ctx, + void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, + int flags), + int ra, int rb, int32_t disp16, int fp, + int clear, int local) { TCGv addr; if (local) @@ -288,9 +289,8 @@ static always_inline void gen_store_mem (DisasContext *ctx, tcg_temp_free(addr); } -static always_inline void gen_bcond (DisasContext *ctx, - TCGCond cond, - int ra, int32_t disp, int mask) +static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra, + int32_t disp, int mask) { int l1, l2; @@ -317,8 +317,8 @@ static always_inline void gen_bcond (DisasContext *ctx, gen_set_label(l2); } -static always_inline void gen_fbcond (DisasContext *ctx, int opc, - int ra, int32_t disp16) +static inline void gen_fbcond(DisasContext *ctx, int opc, int ra, + int32_t disp16) { int l1, l2; TCGv tmp; @@ -363,9 +363,8 @@ static always_inline void gen_fbcond (DisasContext *ctx, int opc, gen_set_label(l2); } -static always_inline void gen_cmov (TCGCond inv_cond, - int ra, int rb, int rc, - int islit, uint8_t lit, int mask) +static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc, + int islit, uint8_t lit, int mask) { int l1; @@ -397,7 +396,7 @@ static always_inline void gen_cmov (TCGCond inv_cond, } #define FARITH2(name) \ -static always_inline void glue(gen_f, name)(int rb, int rc) \ +static inline void glue(gen_f, name)(int rb, int rc) \ { \ if (unlikely(rc == 31)) \ return; \ @@ -429,7 +428,7 @@ FARITH2(cvtqlv) FARITH2(cvtqlsv) #define FARITH3(name) \ -static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ +static inline void glue(gen_f, name)(int ra, int rb, int rc) \ { \ if (unlikely(rc == 31)) \ return; \ @@ -480,7 +479,7 @@ FARITH3(cpysn) FARITH3(cpyse) #define FCMOV(name) \ -static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ +static inline void glue(gen_f, name)(int ra, int rb, int rc) \ { \ int l1; \ TCGv tmp; \ @@ -512,9 +511,8 @@ FCMOV(cmpfle) FCMOV(cmpfgt) /* EXTWH, EXTWH, EXTLH, EXTQH */ -static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), - int ra, int rb, int rc, - int islit, uint8_t lit) +static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1), + int ra, int rb, int rc, int islit, uint8_t lit) { if (unlikely(rc == 31)) return; @@ -543,9 +541,8 @@ static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), } /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */ -static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), - int ra, int rb, int rc, - int islit, uint8_t lit) +static inline void gen_ext_l(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1), + int ra, int rb, int rc, int islit, uint8_t lit) { if (unlikely(rc == 31)) return; @@ -568,8 +565,8 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), /* Code to call arith3 helpers */ #define ARITH3(name) \ -static always_inline void glue(gen_, name) (int ra, int rb, int rc, \ - int islit, uint8_t lit) \ +static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\ + uint8_t lit) \ { \ if (unlikely(rc == 31)) \ return; \ @@ -617,9 +614,8 @@ ARITH3(umulh) ARITH3(mullv) ARITH3(mulqv) -static always_inline void gen_cmp(TCGCond cond, - int ra, int rb, int rc, - int islit, uint8_t lit) +static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit, + uint8_t lit) { int l1, l2; TCGv tmp; @@ -647,7 +643,7 @@ static always_inline void gen_cmp(TCGCond cond, gen_set_label(l2); } -static always_inline int translate_one (DisasContext *ctx, uint32_t insn) +static inline int translate_one(DisasContext *ctx, uint32_t insn) { uint32_t palcode; int32_t disp21, disp16, disp12; @@ -2336,9 +2332,9 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) return ret; } -static always_inline void gen_intermediate_code_internal (CPUState *env, - TranslationBlock *tb, - int search_pc) +static inline void gen_intermediate_code_internal(CPUState *env, + TranslationBlock *tb, + int search_pc) { #if defined ALPHA_DEBUG_DISAS static int insn_count; diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 8c1029e6f9..6f37f4be7b 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -781,7 +781,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid); #endif #endif -static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn) +static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) { uint64_t gprv; diff --git a/target-ppc/exec.h b/target-ppc/exec.h index 0481eb235c..ef1e44bda4 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -35,21 +35,21 @@ register struct CPUPPCState *env asm(AREG0); #include "softmmu_exec.h" #endif /* !defined(CONFIG_USER_ONLY) */ -static always_inline void env_to_regs (void) +static inline void env_to_regs(void) { } -static always_inline void regs_to_env (void) +static inline void regs_to_env(void) { } -static always_inline int cpu_has_work(CPUState *env) +static inline int cpu_has_work(CPUState *env) { return (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)); } -static always_inline int cpu_halted (CPUState *env) +static inline int cpu_halted(CPUState *env) { if (!env->halted) return 0; diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 6eca2e53c3..281b56a479 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -104,23 +104,23 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) #else /* Common routines used by software and hardware TLBs emulation */ -static always_inline int pte_is_valid (target_ulong pte0) +static inline int pte_is_valid(target_ulong pte0) { return pte0 & 0x80000000 ? 1 : 0; } -static always_inline void pte_invalidate (target_ulong *pte0) +static inline void pte_invalidate(target_ulong *pte0) { *pte0 &= ~0x80000000; } #if defined(TARGET_PPC64) -static always_inline int pte64_is_valid (target_ulong pte0) +static inline int pte64_is_valid(target_ulong pte0) { return pte0 & 0x0000000000000001ULL ? 1 : 0; } -static always_inline void pte64_invalidate (target_ulong *pte0) +static inline void pte64_invalidate(target_ulong *pte0) { *pte0 &= ~0x0000000000000001ULL; } @@ -133,7 +133,7 @@ static always_inline void pte64_invalidate (target_ulong *pte0) #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) #endif -static always_inline int pp_check (int key, int pp, int nx) +static inline int pp_check(int key, int pp, int nx) { int access; @@ -173,7 +173,7 @@ static always_inline int pp_check (int key, int pp, int nx) return access; } -static always_inline int check_prot (int prot, int rw, int access_type) +static inline int check_prot(int prot, int rw, int access_type) { int ret; @@ -197,9 +197,8 @@ static always_inline int check_prot (int prot, int rw, int access_type) return ret; } -static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, - target_ulong pte0, target_ulong pte1, - int h, int rw, int type) +static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0, + target_ulong pte1, int h, int rw, int type) { target_ulong ptem, mmask; int access, ret, pteh, ptev, pp; @@ -260,24 +259,22 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, return ret; } -static always_inline int pte32_check (mmu_ctx_t *ctx, - target_ulong pte0, target_ulong pte1, - int h, int rw, int type) +static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0, + target_ulong pte1, int h, int rw, int type) { return _pte_check(ctx, 0, pte0, pte1, h, rw, type); } #if defined(TARGET_PPC64) -static always_inline int pte64_check (mmu_ctx_t *ctx, - target_ulong pte0, target_ulong pte1, - int h, int rw, int type) +static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0, + target_ulong pte1, int h, int rw, int type) { return _pte_check(ctx, 1, pte0, pte1, h, rw, type); } #endif -static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, - int ret, int rw) +static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, + int ret, int rw) { int store = 0; @@ -302,8 +299,8 @@ static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, } /* Software driven TLB helpers */ -static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, - int way, int is_code) +static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way, + int is_code) { int nr; @@ -318,7 +315,7 @@ static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, return nr; } -static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) +static inline void ppc6xx_tlb_invalidate_all(CPUState *env) { ppc6xx_tlb_t *tlb; int nr, max; @@ -335,10 +332,9 @@ static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) tlb_flush(env, 1); } -static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, - target_ulong eaddr, - int is_code, - int match_epn) +static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env, + target_ulong eaddr, + int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) ppc6xx_tlb_t *tlb; @@ -361,9 +357,8 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, #endif } -static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, - target_ulong eaddr, - int is_code) +static inline void ppc6xx_tlb_invalidate_virt(CPUState *env, + target_ulong eaddr, int is_code) { __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0); } @@ -387,9 +382,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, env->last_way = way; } -static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, - int access_type) +static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx, + target_ulong eaddr, int rw, int access_type) { ppc6xx_tlb_t *tlb; int nr, best, way; @@ -452,9 +446,9 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, } /* Perform BAT hit & translation */ -static always_inline void bat_size_prot (CPUState *env, target_ulong *blp, - int *validp, int *protp, - target_ulong *BATu, target_ulong *BATl) +static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp, + int *protp, target_ulong *BATu, + target_ulong *BATl) { target_ulong bl; int pp, valid, prot; @@ -477,10 +471,9 @@ static always_inline void bat_size_prot (CPUState *env, target_ulong *blp, *protp = prot; } -static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, - int *validp, int *protp, - target_ulong *BATu, - target_ulong *BATl) +static inline void bat_601_size_prot(CPUState *env, target_ulong *blp, + int *validp, int *protp, + target_ulong *BATu, target_ulong *BATl) { target_ulong bl; int key, pp, valid, prot; @@ -503,8 +496,8 @@ static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, *protp = prot; } -static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, - target_ulong virtual, int rw, int type) +static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual, + int rw, int type) { target_ulong *BATlt, *BATut, *BATu, *BATl; target_ulong base, BEPIl, BEPIu, bl; @@ -579,9 +572,8 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, } /* PTE table lookup */ -static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, - int rw, int type, - int target_page_bits) +static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw, + int type, int target_page_bits) { target_ulong base, pte0, pte1; int i, good = -1; @@ -664,23 +656,22 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, return ret; } -static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, - int type, int target_page_bits) +static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type, + int target_page_bits) { return _find_pte(ctx, 0, h, rw, type, target_page_bits); } #if defined(TARGET_PPC64) -static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, - int type, int target_page_bits) +static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type, + int target_page_bits) { return _find_pte(ctx, 1, h, rw, type, target_page_bits); } #endif -static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, - int h, int rw, int type, - int target_page_bits) +static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw, + int type, int target_page_bits) { #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) @@ -721,20 +712,19 @@ static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb) entry->tmp = slb->tmp; } -static always_inline int slb_is_valid (ppc_slb_t *slb) +static inline int slb_is_valid(ppc_slb_t *slb) { return (int)(slb->tmp64 & 0x0000000008000000ULL); } -static always_inline void slb_invalidate (ppc_slb_t *slb) +static inline void slb_invalidate(ppc_slb_t *slb) { slb->tmp64 &= ~0x0000000008000000ULL; } -static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, - target_ulong *vsid, - target_ulong *page_mask, int *attr, - int *target_page_bits) +static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr, + target_ulong *vsid, target_ulong *page_mask, + int *attr, int *target_page_bits) { target_ulong mask; int n, ret; @@ -868,16 +858,16 @@ void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs) #endif /* defined(TARGET_PPC64) */ /* Perform segment based translation */ -static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1, - int sdr_sh, - target_phys_addr_t hash, - target_phys_addr_t mask) +static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1, + int sdr_sh, + target_phys_addr_t hash, + target_phys_addr_t mask) { return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); } -static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int type) +static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, + target_ulong eaddr, int rw, int type) { target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; target_ulong sr, vsid, vsid_mask, pgidx, page_mask; @@ -1063,10 +1053,10 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, } /* Generic TLB check function for embedded PowerPC implementations */ -static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, - target_phys_addr_t *raddrp, - target_ulong address, - uint32_t pid, int ext, int i) +static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb, + target_phys_addr_t *raddrp, + target_ulong address, uint32_t pid, int ext, + int i) { target_ulong mask; @@ -1117,7 +1107,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid) } /* Helpers specific to PowerPC 40x implementations */ -static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) +static inline void ppc4xx_tlb_invalidate_all(CPUState *env) { ppcemb_tlb_t *tlb; int i; @@ -1129,9 +1119,8 @@ static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) tlb_flush(env, 1); } -static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, - target_ulong eaddr, - uint32_t pid) +static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, + target_ulong eaddr, uint32_t pid) { #if !defined(FLUSH_ALL_TLBS) ppcemb_tlb_t *tlb; @@ -1270,8 +1259,8 @@ static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, return ret; } -static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw) +static inline int check_physical(CPUState *env, mmu_ctx_t *ctx, + target_ulong eaddr, int rw) { int in_plb, ret; @@ -1674,9 +1663,8 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, /*****************************************************************************/ /* BATs management */ #if !defined(FLUSH_ALL_TLBS) -static always_inline void do_invalidate_BAT (CPUPPCState *env, - target_ulong BATu, - target_ulong mask) +static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, + target_ulong mask) { target_ulong base, end, page; @@ -1690,8 +1678,8 @@ static always_inline void do_invalidate_BAT (CPUPPCState *env, } #endif -static always_inline void dump_store_bat (CPUPPCState *env, char ID, - int ul, int nr, target_ulong value) +static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr, + target_ulong value) { LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n", ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); @@ -2046,7 +2034,7 @@ void ppc_hw_interrupt (CPUState *env) env->error_code = 0; } #else /* defined (CONFIG_USER_ONLY) */ -static always_inline void dump_syscall (CPUState *env) +static inline void dump_syscall(CPUState *env) { qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX " r5=" REGX " r6=" REGX " nip=" ADDRX "\n", @@ -2057,8 +2045,7 @@ static always_inline void dump_syscall (CPUState *env) /* Note that this function should be greatly optimized * when called with a constant excp, from ppc_hw_interrupt */ -static always_inline void powerpc_excp (CPUState *env, - int excp_model, int excp) +static inline void powerpc_excp(CPUState *env, int excp_model, int excp) { target_ulong msr, new_msr, vector; int srr0, srr1, asrr0, asrr1; diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index 2a1f541d11..3c988502ed 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -21,7 +21,7 @@ #define __HELPER_REGS_H__ /* Swap temporary saved registers with GPRs */ -static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env) +static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) { target_ulong tmp; @@ -39,7 +39,7 @@ static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env) env->tgpr[3] = tmp; } -static always_inline void hreg_compute_mem_idx (CPUPPCState *env) +static inline void hreg_compute_mem_idx(CPUPPCState *env) { /* Precompute MMU index */ if (msr_pr == 0 && msr_hv != 0) { @@ -49,7 +49,7 @@ static always_inline void hreg_compute_mem_idx (CPUPPCState *env) } } -static always_inline void hreg_compute_hflags (CPUPPCState *env) +static inline void hreg_compute_hflags(CPUPPCState *env) { target_ulong hflags_mask; @@ -64,8 +64,8 @@ static always_inline void hreg_compute_hflags (CPUPPCState *env) env->hflags |= env->hflags_nmsr; } -static always_inline int hreg_store_msr (CPUPPCState *env, target_ulong value, - int alter_hv) +static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, + int alter_hv) { int excp; diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index 812282c746..d8caac0c81 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -239,7 +239,7 @@ void helper_store_601_batu (uint32_t nr, target_ulong val) /*****************************************************************************/ /* Memory load and stores */ -static always_inline target_ulong addr_add(target_ulong addr, target_long arg) +static inline target_ulong addr_add(target_ulong addr, target_long arg) { #if defined(TARGET_PPC64) if (!msr_sf) @@ -532,7 +532,7 @@ uint32_t helper_float64_to_float32(uint64_t arg) return f.l; } -static always_inline int isden (float64 d) +static inline int isden(float64 d) { CPU_DoubleU u; @@ -594,7 +594,7 @@ uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf) } /* Floating-point invalid operations exception */ -static always_inline uint64_t fload_invalid_op_excp (int op) +static inline uint64_t fload_invalid_op_excp(int op) { uint64_t ret = 0; int ve; @@ -675,7 +675,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op) return ret; } -static always_inline void float_zero_divide_excp (void) +static inline void float_zero_divide_excp(void) { env->fpscr |= 1 << FPSCR_ZX; env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); @@ -691,7 +691,7 @@ static always_inline void float_zero_divide_excp (void) } } -static always_inline void float_overflow_excp (void) +static inline void float_overflow_excp(void) { env->fpscr |= 1 << FPSCR_OX; /* Update the floating-point exception summary */ @@ -709,7 +709,7 @@ static always_inline void float_overflow_excp (void) } } -static always_inline void float_underflow_excp (void) +static inline void float_underflow_excp(void) { env->fpscr |= 1 << FPSCR_UX; /* Update the floating-point exception summary */ @@ -724,7 +724,7 @@ static always_inline void float_underflow_excp (void) } } -static always_inline void float_inexact_excp (void) +static inline void float_inexact_excp(void) { env->fpscr |= 1 << FPSCR_XX; /* Update the floating-point exception summary */ @@ -738,7 +738,7 @@ static always_inline void float_inexact_excp (void) } } -static always_inline void fpscr_set_rounding_mode (void) +static inline void fpscr_set_rounding_mode(void) { int rnd_type; @@ -1199,7 +1199,7 @@ uint64_t helper_fctidz (uint64_t arg) #endif -static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode) +static inline uint64_t do_fri(uint64_t arg, int rounding_mode) { CPU_DoubleU farg; farg.ll = arg; @@ -1614,8 +1614,8 @@ void helper_store_msr (target_ulong val) } } -static always_inline void do_rfi (target_ulong nip, target_ulong msr, - target_ulong msrm, int keep_msrh) +static inline void do_rfi(target_ulong nip, target_ulong msr, + target_ulong msrm, int keep_msrh) { #if defined(TARGET_PPC64) if (msr & (1ULL << MSR_SF)) { @@ -1956,7 +1956,7 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_ /* Saturating arithmetic helpers. */ #define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \ - static always_inline to_type cvt##from##to (from_type x, int *sat) \ + static inline to_type cvt##from##to(from_type x, int *sat) \ { \ to_type r; \ if (use_min && x < min) { \ @@ -1975,7 +1975,7 @@ SATCVT(sw, sh, int32_t, int16_t, INT16_MIN, INT16_MAX, 1, 1) SATCVT(sd, sw, int64_t, int32_t, INT32_MIN, INT32_MAX, 1, 1) /* Work around gcc problems with the macro version */ -static always_inline uint8_t cvtuhub(uint16_t x, int *sat) +static inline uint8_t cvtuhub(uint16_t x, int *sat) { uint8_t r; @@ -2243,8 +2243,8 @@ VCMPFP(gtfp, ==, float_relation_greater) #undef VCMPFP_DO #undef VCMPFP -static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a, - ppc_avr_t *b, int record) +static inline void vcmpbfp_internal(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, + int record) { int i; int all_in = 0; @@ -3063,12 +3063,12 @@ static uint8_t hbrev[16] = { 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF, }; -static always_inline uint8_t byte_reverse (uint8_t val) +static inline uint8_t byte_reverse(uint8_t val) { return hbrev[val >> 4] | (hbrev[val & 0xF] << 4); } -static always_inline uint32_t word_reverse (uint32_t val) +static inline uint32_t word_reverse(uint32_t val) { return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) | (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24); @@ -3100,7 +3100,7 @@ uint32_t helper_cntlzw32 (uint32_t val) } /* Single-precision floating-point conversions */ -static always_inline uint32_t efscfsi (uint32_t val) +static inline uint32_t efscfsi(uint32_t val) { CPU_FloatU u; @@ -3109,7 +3109,7 @@ static always_inline uint32_t efscfsi (uint32_t val) return u.l; } -static always_inline uint32_t efscfui (uint32_t val) +static inline uint32_t efscfui(uint32_t val) { CPU_FloatU u; @@ -3118,7 +3118,7 @@ static always_inline uint32_t efscfui (uint32_t val) return u.l; } -static always_inline int32_t efsctsi (uint32_t val) +static inline int32_t efsctsi(uint32_t val) { CPU_FloatU u; @@ -3130,7 +3130,7 @@ static always_inline int32_t efsctsi (uint32_t val) return float32_to_int32(u.f, &env->vec_status); } -static always_inline uint32_t efsctui (uint32_t val) +static inline uint32_t efsctui(uint32_t val) { CPU_FloatU u; @@ -3142,7 +3142,7 @@ static always_inline uint32_t efsctui (uint32_t val) return float32_to_uint32(u.f, &env->vec_status); } -static always_inline uint32_t efsctsiz (uint32_t val) +static inline uint32_t efsctsiz(uint32_t val) { CPU_FloatU u; @@ -3154,7 +3154,7 @@ static always_inline uint32_t efsctsiz (uint32_t val) return float32_to_int32_round_to_zero(u.f, &env->vec_status); } -static always_inline uint32_t efsctuiz (uint32_t val) +static inline uint32_t efsctuiz(uint32_t val) { CPU_FloatU u; @@ -3166,7 +3166,7 @@ static always_inline uint32_t efsctuiz (uint32_t val) return float32_to_uint32_round_to_zero(u.f, &env->vec_status); } -static always_inline uint32_t efscfsf (uint32_t val) +static inline uint32_t efscfsf(uint32_t val) { CPU_FloatU u; float32 tmp; @@ -3178,7 +3178,7 @@ static always_inline uint32_t efscfsf (uint32_t val) return u.l; } -static always_inline uint32_t efscfuf (uint32_t val) +static inline uint32_t efscfuf(uint32_t val) { CPU_FloatU u; float32 tmp; @@ -3190,7 +3190,7 @@ static always_inline uint32_t efscfuf (uint32_t val) return u.l; } -static always_inline uint32_t efsctsf (uint32_t val) +static inline uint32_t efsctsf(uint32_t val) { CPU_FloatU u; float32 tmp; @@ -3205,7 +3205,7 @@ static always_inline uint32_t efsctsf (uint32_t val) return float32_to_int32(u.f, &env->vec_status); } -static always_inline uint32_t efsctuf (uint32_t val) +static inline uint32_t efsctuf(uint32_t val) { CPU_FloatU u; float32 tmp; @@ -3274,7 +3274,7 @@ HELPER_SPE_VECTOR_CONV(fsctsf); HELPER_SPE_VECTOR_CONV(fsctuf); /* Single-precision floating-point arithmetic */ -static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2) +static inline uint32_t efsadd(uint32_t op1, uint32_t op2) { CPU_FloatU u1, u2; u1.l = op1; @@ -3283,7 +3283,7 @@ static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2) return u1.l; } -static always_inline uint32_t efssub (uint32_t op1, uint32_t op2) +static inline uint32_t efssub(uint32_t op1, uint32_t op2) { CPU_FloatU u1, u2; u1.l = op1; @@ -3292,7 +3292,7 @@ static always_inline uint32_t efssub (uint32_t op1, uint32_t op2) return u1.l; } -static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2) +static inline uint32_t efsmul(uint32_t op1, uint32_t op2) { CPU_FloatU u1, u2; u1.l = op1; @@ -3301,7 +3301,7 @@ static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2) return u1.l; } -static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2) +static inline uint32_t efsdiv(uint32_t op1, uint32_t op2) { CPU_FloatU u1, u2; u1.l = op1; @@ -3340,7 +3340,7 @@ HELPER_SPE_VECTOR_ARITH(fsmul); HELPER_SPE_VECTOR_ARITH(fsdiv); /* Single-precision floating-point comparisons */ -static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2) +static inline uint32_t efststlt(uint32_t op1, uint32_t op2) { CPU_FloatU u1, u2; u1.l = op1; @@ -3348,7 +3348,7 @@ static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2) return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0; } -static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2) +static inline uint32_t efststgt(uint32_t op1, uint32_t op2) { CPU_FloatU u1, u2; u1.l = op1; @@ -3356,7 +3356,7 @@ static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2) return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4; } -static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2) +static inline uint32_t efststeq(uint32_t op1, uint32_t op2) { CPU_FloatU u1, u2; u1.l = op1; @@ -3364,19 +3364,19 @@ static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2) return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0; } -static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2) +static inline uint32_t efscmplt(uint32_t op1, uint32_t op2) { /* XXX: TODO: test special values (NaN, infinites, ...) */ return efststlt(op1, op2); } -static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2) +static inline uint32_t efscmpgt(uint32_t op1, uint32_t op2) { /* XXX: TODO: test special values (NaN, infinites, ...) */ return efststgt(op1, op2); } -static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2) +static inline uint32_t efscmpeq(uint32_t op1, uint32_t op2) { /* XXX: TODO: test special values (NaN, infinites, ...) */ return efststeq(op1, op2); @@ -3400,7 +3400,7 @@ HELPER_SINGLE_SPE_CMP(fscmpgt); /* efscmpeq */ HELPER_SINGLE_SPE_CMP(fscmpeq); -static always_inline uint32_t evcmp_merge (int t0, int t1) +static inline uint32_t evcmp_merge(int t0, int t1) { return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1); } @@ -3850,12 +3850,12 @@ void helper_74xx_tlbi (target_ulong EPN) do_74xx_tlb(EPN, 1); } -static always_inline target_ulong booke_tlb_to_page_size (int size) +static inline target_ulong booke_tlb_to_page_size(int size) { return 1024 << (2 * size); } -static always_inline int booke_page_size_to_tlb (target_ulong page_size) +static inline int booke_page_size_to_tlb(target_ulong page_size) { int size; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f82c6e5bae..92e5713d9c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -210,14 +210,14 @@ struct opc_handler_t { #endif }; -static always_inline void gen_reset_fpstatus (void) +static inline void gen_reset_fpstatus(void) { #ifdef CONFIG_SOFTFLOAT gen_helper_reset_fpstatus(); #endif } -static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc) +static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) { TCGv_i32 t0 = tcg_temp_new_i32(); @@ -239,7 +239,7 @@ static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_ tcg_temp_free_i32(t0); } -static always_inline void gen_set_access_type (DisasContext *ctx, int access_type) +static inline void gen_set_access_type(DisasContext *ctx, int access_type) { if (ctx->access_type != access_type) { tcg_gen_movi_i32(cpu_access_type, access_type); @@ -247,7 +247,7 @@ static always_inline void gen_set_access_type (DisasContext *ctx, int access_typ } } -static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) +static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) { #if defined(TARGET_PPC64) if (ctx->sf_mode) @@ -257,7 +257,7 @@ static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); } -static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error) +static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) { TCGv_i32 t0, t1; if (ctx->exception == POWERPC_EXCP_NONE) { @@ -271,7 +271,7 @@ static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, u ctx->exception = (excp); } -static always_inline void gen_exception (DisasContext *ctx, uint32_t excp) +static inline void gen_exception(DisasContext *ctx, uint32_t excp) { TCGv_i32 t0; if (ctx->exception == POWERPC_EXCP_NONE) { @@ -283,7 +283,7 @@ static always_inline void gen_exception (DisasContext *ctx, uint32_t excp) ctx->exception = (excp); } -static always_inline void gen_debug_exception (DisasContext *ctx) +static inline void gen_debug_exception(DisasContext *ctx) { TCGv_i32 t0; @@ -294,20 +294,20 @@ static always_inline void gen_debug_exception (DisasContext *ctx) tcg_temp_free_i32(t0); } -static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error) +static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) { gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); } /* Stop translation */ -static always_inline void gen_stop_exception (DisasContext *ctx) +static inline void gen_stop_exception(DisasContext *ctx) { gen_update_nip(ctx, ctx->nip); ctx->exception = POWERPC_EXCP_STOP; } /* No need to update nip here, as execution flow will change */ -static always_inline void gen_sync_exception (DisasContext *ctx) +static inline void gen_sync_exception(DisasContext *ctx) { ctx->exception = POWERPC_EXCP_SYNC; } @@ -332,13 +332,13 @@ typedef struct opcode_t { /*****************************************************************************/ /*** Instruction decoding ***/ #define EXTRACT_HELPER(name, shift, nb) \ -static always_inline uint32_t name (uint32_t opcode) \ +static inline uint32_t name(uint32_t opcode) \ { \ return (opcode >> (shift)) & ((1 << (nb)) - 1); \ } #define EXTRACT_SHELPER(name, shift, nb) \ -static always_inline int32_t name (uint32_t opcode) \ +static inline int32_t name(uint32_t opcode) \ { \ return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ } @@ -369,7 +369,7 @@ EXTRACT_HELPER(crbA, 16, 5); EXTRACT_HELPER(crbB, 11, 5); /* SPR / TBL */ EXTRACT_HELPER(_SPR, 11, 10); -static always_inline uint32_t SPR (uint32_t opcode) +static inline uint32_t SPR(uint32_t opcode) { uint32_t sprn = _SPR(opcode); @@ -407,12 +407,12 @@ EXTRACT_HELPER(FPIMM, 12, 4); /* Displacement */ EXTRACT_SHELPER(d, 0, 16); /* Immediate address */ -static always_inline target_ulong LI (uint32_t opcode) +static inline target_ulong LI(uint32_t opcode) { return (opcode >> 0) & 0x03FFFFFC; } -static always_inline uint32_t BD (uint32_t opcode) +static inline uint32_t BD(uint32_t opcode) { return (opcode >> 0) & 0xFFFC; } @@ -425,7 +425,7 @@ EXTRACT_HELPER(AA, 1, 1); EXTRACT_HELPER(LK, 0, 1); /* Create a mask between <start> and <end> bits */ -static always_inline target_ulong MASK (uint32_t start, uint32_t end) +static inline target_ulong MASK(uint32_t start, uint32_t end) { target_ulong ret; @@ -514,12 +514,12 @@ static always_inline target_ulong MASK (uint32_t start, uint32_t end) #endif /* SPR load/store helpers */ -static always_inline void gen_load_spr(TCGv t, int reg) +static inline void gen_load_spr(TCGv t, int reg) { tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); } -static always_inline void gen_store_spr(int reg, TCGv t) +static inline void gen_store_spr(int reg, TCGv t) { tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); } @@ -538,7 +538,7 @@ static opc_handler_t invalid_handler = { /*** Integer comparison ***/ -static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) +static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) { int l1, l2, l3; @@ -566,7 +566,7 @@ static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) gen_set_label(l3); } -static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) +static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) { TCGv t0 = tcg_const_local_tl(arg1); gen_op_cmp(arg0, t0, s, crf); @@ -574,7 +574,7 @@ static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int c } #if defined(TARGET_PPC64) -static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) +static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) { TCGv t0, t1; t0 = tcg_temp_local_new(); @@ -591,7 +591,7 @@ static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) tcg_temp_free(t0); } -static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) +static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) { TCGv t0 = tcg_const_local_tl(arg1); gen_op_cmp32(arg0, t0, s, crf); @@ -599,7 +599,7 @@ static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int } #endif -static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg) +static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) { #if defined(TARGET_PPC64) if (!(ctx->sf_mode)) @@ -689,7 +689,8 @@ static void gen_isel(DisasContext *ctx) /*** Integer arithmetic ***/ -static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub) +static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, + TCGv arg1, TCGv arg2, int sub) { int l1; TCGv t0; @@ -721,7 +722,8 @@ static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, tcg_temp_free(t0); } -static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub) +static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, + TCGv arg2, int sub) { int l1 = gen_new_label(); @@ -756,8 +758,9 @@ static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, } /* Common add function */ -static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, - int add_ca, int compute_ca, int compute_ov) +static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, + TCGv arg2, int add_ca, int compute_ca, + int compute_ov) { TCGv t0, t1; @@ -857,8 +860,8 @@ static void gen_addi(DisasContext *ctx) } } /* addic addic.*/ -static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1, - int compute_Rc0) +static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1, + int compute_Rc0) { target_long simm = SIMM(ctx->opcode); @@ -902,8 +905,8 @@ static void gen_addis(DisasContext *ctx) } } -static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, - int sign, int compute_ov) +static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, + TCGv arg2, int sign, int compute_ov) { int l1 = gen_new_label(); int l2 = gen_new_label(); @@ -957,8 +960,8 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); #if defined(TARGET_PPC64) -static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, - int sign, int compute_ov) +static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, + TCGv arg2, int sign, int compute_ov) { int l1 = gen_new_label(); int l2 = gen_new_label(); @@ -1133,7 +1136,8 @@ GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17); #endif /* neg neg. nego nego. */ -static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check) +static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, + int ov_check) { int l1 = gen_new_label(); int l2 = gen_new_label(); @@ -1175,8 +1179,9 @@ static void gen_nego(DisasContext *ctx) } /* Common subf function */ -static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, - int add_ca, int compute_ca, int compute_ov) +static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, + TCGv arg2, int add_ca, int compute_ca, + int compute_ov) { TCGv t0, t1; @@ -1658,8 +1663,8 @@ static void glue(gen_, name##3)(DisasContext *ctx) \ gen_##name(ctx, 1, 1); \ } -static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, - uint32_t me, uint32_t sh) +static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, + uint32_t sh) { if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); @@ -1679,7 +1684,7 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } /* rldicl - rldicl. */ -static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) +static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) { uint32_t sh, mb; @@ -1689,7 +1694,7 @@ static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) } GEN_PPC64_R4(rldicl, 0x1E, 0x00); /* rldicr - rldicr. */ -static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) +static inline void gen_rldicr(DisasContext *ctx, int men, int shn) { uint32_t sh, me; @@ -1699,7 +1704,7 @@ static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) } GEN_PPC64_R4(rldicr, 0x1E, 0x02); /* rldic - rldic. */ -static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) +static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) { uint32_t sh, mb; @@ -1709,8 +1714,7 @@ static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) } GEN_PPC64_R4(rldic, 0x1E, 0x04); -static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, - uint32_t me) +static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) { TCGv t0; @@ -1730,7 +1734,7 @@ static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, } /* rldcl - rldcl. */ -static always_inline void gen_rldcl (DisasContext *ctx, int mbn) +static inline void gen_rldcl(DisasContext *ctx, int mbn) { uint32_t mb; @@ -1739,7 +1743,7 @@ static always_inline void gen_rldcl (DisasContext *ctx, int mbn) } GEN_PPC64_R2(rldcl, 0x1E, 0x08); /* rldcr - rldcr. */ -static always_inline void gen_rldcr (DisasContext *ctx, int men) +static inline void gen_rldcr(DisasContext *ctx, int men) { uint32_t me; @@ -1748,7 +1752,7 @@ static always_inline void gen_rldcr (DisasContext *ctx, int men) } GEN_PPC64_R2(rldcr, 0x1E, 0x09); /* rldimi - rldimi. */ -static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) +static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) { uint32_t sh, mb, me; @@ -1895,7 +1899,7 @@ static void gen_srad(DisasContext *ctx) gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } /* sradi & sradi. */ -static always_inline void gen_sradi (DisasContext *ctx, int n) +static inline void gen_sradi(DisasContext *ctx, int n) { int sh = SH(ctx->opcode) + (n << 5); if (sh != 0) { @@ -2348,7 +2352,8 @@ static void gen_mtfsfi(DisasContext *ctx) /*** Addressing modes ***/ /* Register indirect with immediate index : EA = (rA|0) + SIMM */ -static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl) +static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, + target_long maskl) { target_long simm = SIMM(ctx->opcode); @@ -2377,7 +2382,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target } } -static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA) +static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) { if (rA(ctx->opcode) == 0) { #if defined(TARGET_PPC64) @@ -2396,7 +2401,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA) } } -static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA) +static inline void gen_addr_register(DisasContext *ctx, TCGv EA) { if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(EA, 0); @@ -2410,7 +2415,8 @@ static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA) } } -static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val) +static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, + target_long val) { tcg_gen_addi_tl(ret, arg1, val); #if defined(TARGET_PPC64) @@ -2420,7 +2426,7 @@ static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, #endif } -static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask) +static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) { int l1 = gen_new_label(); TCGv t0 = tcg_temp_new(); @@ -2439,17 +2445,17 @@ static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask) } /*** Integer load ***/ -static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) { tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); } -static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) { tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); } -static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) { tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); if (unlikely(ctx->le_mode)) { @@ -2457,7 +2463,7 @@ static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2 } } -static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (unlikely(ctx->le_mode)) { tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); @@ -2468,7 +2474,7 @@ static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2 } } -static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) { tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); if (unlikely(ctx->le_mode)) { @@ -2477,7 +2483,7 @@ static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2 } #if defined(TARGET_PPC64) -static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (unlikely(ctx->le_mode)) { tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); @@ -2488,7 +2494,7 @@ static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2 } #endif -static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); if (unlikely(ctx->le_mode)) { @@ -2496,12 +2502,12 @@ static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv a } } -static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) { tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); } -static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (unlikely(ctx->le_mode)) { TCGv t0 = tcg_temp_new(); @@ -2514,7 +2520,7 @@ static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) } } -static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) +static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (unlikely(ctx->le_mode)) { TCGv t0 = tcg_temp_new(); @@ -2527,7 +2533,7 @@ static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) } } -static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { if (unlikely(ctx->le_mode)) { TCGv_i64 t0 = tcg_temp_new_i64(); @@ -2808,7 +2814,7 @@ static void gen_std(DisasContext *ctx) #endif /*** Integer load and store with byte reverse ***/ /* lhbrx */ -static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) +static void inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) { tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); if (likely(!ctx->le_mode)) { @@ -2818,7 +2824,7 @@ static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); /* lwbrx */ -static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) +static void inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) { tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); if (likely(!ctx->le_mode)) { @@ -2828,7 +2834,7 @@ static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); /* sthbrx */ -static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) +static void inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (likely(!ctx->le_mode)) { TCGv t0 = tcg_temp_new(); @@ -2843,7 +2849,7 @@ static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); /* stwbrx */ -static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) +static void inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (likely(!ctx->le_mode)) { TCGv t0 = tcg_temp_new(); @@ -3200,7 +3206,7 @@ GEN_LDUF(name, ldop, op | 0x21, type); \ GEN_LDUXF(name, ldop, op | 0x01, type); \ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) -static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { TCGv t0 = tcg_temp_new(); TCGv_i32 t1 = tcg_temp_new_i32(); @@ -3293,7 +3299,7 @@ GEN_STUF(name, stop, op | 0x21, type); \ GEN_STUXF(name, stop, op | 0x01, type); \ GEN_STXF(name, stop, 0x17, op | 0x00, type) -static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new(); @@ -3310,7 +3316,7 @@ GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); /* Optional: */ -static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { TCGv t0 = tcg_temp_new(); tcg_gen_trunc_i64_tl(t0, arg1), @@ -3321,8 +3327,7 @@ static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCG GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); /*** Branch ***/ -static always_inline void gen_goto_tb (DisasContext *ctx, int n, - target_ulong dest) +static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) { TranslationBlock *tb; tb = ctx->tb; @@ -3354,7 +3359,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n, } } -static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip) +static inline void gen_setlr(DisasContext *ctx, target_ulong nip) { #if defined(TARGET_PPC64) if (ctx->sf_mode == 0) @@ -3390,7 +3395,7 @@ static void gen_b(DisasContext *ctx) #define BCOND_LR 1 #define BCOND_CTR 2 -static always_inline void gen_bcond (DisasContext *ctx, int type) +static inline void gen_bcond(DisasContext *ctx, int type) { uint32_t bo = BO(ctx->opcode); int l1 = gen_new_label(); @@ -3726,7 +3731,7 @@ static void spr_noaccess (void *opaque, int sprn) #endif /* mfspr */ -static always_inline void gen_op_mfspr (DisasContext *ctx) +static inline void gen_op_mfspr(DisasContext *ctx) { void (*read_cb)(void *opaque, int gprn, int sprn); uint32_t sprn = SPR(ctx->opcode); @@ -5333,9 +5338,8 @@ static void gen_tlbiva(DisasContext *ctx) } /* All 405 MAC instructions are translated here */ -static always_inline void gen_405_mulladd_insn (DisasContext *ctx, - int opc2, int opc3, - int ra, int rb, int rt, int Rc) +static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, + int ra, int rb, int rt, int Rc) { TCGv t0, t1; @@ -6015,7 +6019,7 @@ static void gen_icbt_440(DisasContext *ctx) /*** Altivec vector extension ***/ /* Altivec registers moves */ -static always_inline TCGv_ptr gen_avr_ptr(int reg) +static inline TCGv_ptr gen_avr_ptr(int reg) { TCGv_ptr r = tcg_temp_new_ptr(); tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); @@ -6499,7 +6503,8 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) /*** SPE extension ***/ /* Register moves */ -static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) { +static inline void gen_load_gpr64(TCGv_i64 t, int reg) +{ #if defined(TARGET_PPC64) tcg_gen_mov_i64(t, cpu_gpr[reg]); #else @@ -6507,7 +6512,8 @@ static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) { #endif } -static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) { +static inline void gen_store_gpr64(int reg, TCGv_i64 t) +{ #if defined(TARGET_PPC64) tcg_gen_mov_i64(cpu_gpr[reg], t); #else @@ -6529,7 +6535,7 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ } /* Handler for undefined SPE opcodes */ -static always_inline void gen_speundef (DisasContext *ctx) +static inline void gen_speundef(DisasContext *ctx) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); } @@ -6537,7 +6543,7 @@ static always_inline void gen_speundef (DisasContext *ctx) /* SPE logic */ #if defined(TARGET_PPC64) #define GEN_SPEOP_LOGIC2(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6548,7 +6554,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #else #define GEN_SPEOP_LOGIC2(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6573,7 +6579,7 @@ GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); /* SPE logic immediate */ #if defined(TARGET_PPC64) #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6594,7 +6600,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #else #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6614,7 +6620,7 @@ GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); /* SPE arithmetic */ #if defined(TARGET_PPC64) #define GEN_SPEOP_ARITH1(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6635,7 +6641,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #else #define GEN_SPEOP_ARITH1(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6646,7 +6652,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #endif -static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1) +static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) { int l1 = gen_new_label(); int l2 = gen_new_label(); @@ -6662,7 +6668,7 @@ GEN_SPEOP_ARITH1(evabs, gen_op_evabs); GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); -static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1) +static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) { tcg_gen_addi_i32(ret, arg1, 0x8000); tcg_gen_ext16u_i32(ret, ret); @@ -6673,7 +6679,7 @@ GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); #if defined(TARGET_PPC64) #define GEN_SPEOP_ARITH2(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6699,7 +6705,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #else #define GEN_SPEOP_ARITH2(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6712,7 +6718,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #endif -static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { TCGv_i32 t0; int l1, l2; @@ -6731,7 +6737,7 @@ static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); -static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { TCGv_i32 t0; int l1, l2; @@ -6750,7 +6756,7 @@ static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); -static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { TCGv_i32 t0; int l1, l2; @@ -6769,7 +6775,7 @@ static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evslw, gen_op_evslw); -static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_andi_i32(t0, arg2, 0x1F); @@ -6777,7 +6783,7 @@ static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); -static always_inline void gen_evmergehi (DisasContext *ctx) +static inline void gen_evmergehi(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -6797,7 +6803,7 @@ static always_inline void gen_evmergehi (DisasContext *ctx) #endif } GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); -static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_sub_i32(ret, arg2, arg1); } @@ -6806,7 +6812,7 @@ GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); /* SPE arithmetic immediate */ #if defined(TARGET_PPC64) #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6827,7 +6833,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #else #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6845,7 +6851,7 @@ GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); /* SPE comparison */ #if defined(TARGET_PPC64) #define GEN_SPEOP_COMP(name, tcg_cond) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6885,7 +6891,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #else #define GEN_SPEOP_COMP(name, tcg_cond) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -6922,13 +6928,13 @@ GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); /* SPE misc */ -static always_inline void gen_brinc (DisasContext *ctx) +static inline void gen_brinc(DisasContext *ctx) { /* Note: brinc is usable even if SPE is disabled */ gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); } -static always_inline void gen_evmergelo (DisasContext *ctx) +static inline void gen_evmergelo(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -6947,7 +6953,7 @@ static always_inline void gen_evmergelo (DisasContext *ctx) tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); #endif } -static always_inline void gen_evmergehilo (DisasContext *ctx) +static inline void gen_evmergehilo(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -6966,7 +6972,7 @@ static always_inline void gen_evmergehilo (DisasContext *ctx) tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); #endif } -static always_inline void gen_evmergelohi (DisasContext *ctx) +static inline void gen_evmergelohi(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -6993,7 +6999,7 @@ static always_inline void gen_evmergelohi (DisasContext *ctx) } #endif } -static always_inline void gen_evsplati (DisasContext *ctx) +static inline void gen_evsplati(DisasContext *ctx) { uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; @@ -7004,7 +7010,7 @@ static always_inline void gen_evsplati (DisasContext *ctx) tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); #endif } -static always_inline void gen_evsplatfi (DisasContext *ctx) +static inline void gen_evsplatfi(DisasContext *ctx) { uint64_t imm = rA(ctx->opcode) << 11; @@ -7016,7 +7022,7 @@ static always_inline void gen_evsplatfi (DisasContext *ctx) #endif } -static always_inline void gen_evsel (DisasContext *ctx) +static inline void gen_evsel(DisasContext *ctx) { int l1 = gen_new_label(); int l2 = gen_new_label(); @@ -7112,7 +7118,7 @@ GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// /* SPE load and stores */ -static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh) +static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) { target_ulong uimm = rB(ctx->opcode); @@ -7128,7 +7134,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, in } } -static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr) +static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); @@ -7142,7 +7148,7 @@ static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr) #endif } -static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr) +static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) TCGv t0 = tcg_temp_new(); @@ -7159,7 +7165,7 @@ static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr) #endif } -static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr) +static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) @@ -7192,7 +7198,7 @@ static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); gen_qemu_ld16u(ctx, t0, addr); @@ -7208,7 +7214,7 @@ static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); gen_qemu_ld16u(ctx, t0, addr); @@ -7222,7 +7228,7 @@ static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); gen_qemu_ld16s(ctx, t0, addr); @@ -7237,7 +7243,7 @@ static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) @@ -7257,7 +7263,7 @@ static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) TCGv t0 = tcg_temp_new(); @@ -7274,7 +7280,7 @@ static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) #endif } -static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) TCGv t0 = tcg_temp_new(); @@ -7292,7 +7298,7 @@ static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) #endif } -static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); gen_qemu_ld32u(ctx, t0, addr); @@ -7306,7 +7312,7 @@ static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) +static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) @@ -7331,7 +7337,7 @@ static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) +static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); @@ -7343,7 +7349,7 @@ static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) #endif } -static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) +static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) TCGv t0 = tcg_temp_new(); @@ -7357,7 +7363,7 @@ static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); } -static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) +static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) @@ -7381,7 +7387,7 @@ static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); } -static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) +static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) { TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) @@ -7396,7 +7402,7 @@ static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) tcg_temp_free(t0); } -static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) +static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) TCGv t0 = tcg_temp_new(); @@ -7410,7 +7416,7 @@ static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); } -static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) +static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) { #if defined(TARGET_PPC64) TCGv t0 = tcg_temp_new(); @@ -7422,7 +7428,7 @@ static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) #endif } -static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) +static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) { gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); } @@ -7545,7 +7551,7 @@ GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE); /*** SPE floating-point extension ***/ #if defined(TARGET_PPC64) #define GEN_SPEFPUOP_CONV_32_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i32 t0; \ TCGv t1; \ @@ -7561,7 +7567,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free(t1); \ } #define GEN_SPEFPUOP_CONV_32_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i32 t0; \ TCGv t1; \ @@ -7576,7 +7582,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free(t1); \ } #define GEN_SPEFPUOP_CONV_64_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i32 t0 = tcg_temp_new_i32(); \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ @@ -7584,12 +7590,12 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free_i32(t0); \ } #define GEN_SPEFPUOP_CONV_64_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ } #define GEN_SPEFPUOP_ARITH2_32_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i32 t0, t1; \ TCGv_i64 t2; \ @@ -7612,7 +7618,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free(t2); \ } #define GEN_SPEFPUOP_ARITH2_64_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -7622,7 +7628,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ cpu_gpr[rB(ctx->opcode)]); \ } #define GEN_SPEFPUOP_COMP_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i32 t0, t1; \ if (unlikely(!ctx->spe_enabled)) { \ @@ -7638,7 +7644,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free_i32(t1); \ } #define GEN_SPEFPUOP_COMP_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -7649,12 +7655,12 @@ static always_inline void gen_##name (DisasContext *ctx) \ } #else #define GEN_SPEFPUOP_CONV_32_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ } #define GEN_SPEFPUOP_CONV_32_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i64 t0 = tcg_temp_new_i64(); \ gen_load_gpr64(t0, rB(ctx->opcode)); \ @@ -7662,7 +7668,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free_i64(t0); \ } #define GEN_SPEFPUOP_CONV_64_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i64 t0 = tcg_temp_new_i64(); \ gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ @@ -7670,7 +7676,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free_i64(t0); \ } #define GEN_SPEFPUOP_CONV_64_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i64 t0 = tcg_temp_new_i64(); \ gen_load_gpr64(t0, rB(ctx->opcode)); \ @@ -7679,7 +7685,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free_i64(t0); \ } #define GEN_SPEFPUOP_ARITH2_32_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -7689,7 +7695,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ } #define GEN_SPEFPUOP_ARITH2_64_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i64 t0, t1; \ if (unlikely(!ctx->spe_enabled)) { \ @@ -7706,7 +7712,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ tcg_temp_free_i64(t1); \ } #define GEN_SPEFPUOP_COMP_32(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ if (unlikely(!ctx->spe_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_APU); \ @@ -7716,7 +7722,7 @@ static always_inline void gen_##name (DisasContext *ctx) \ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ } #define GEN_SPEFPUOP_COMP_64(name) \ -static always_inline void gen_##name (DisasContext *ctx) \ +static inline void gen_##name(DisasContext *ctx) \ { \ TCGv_i64 t0, t1; \ if (unlikely(!ctx->spe_enabled)) { \ @@ -7739,7 +7745,7 @@ GEN_SPEFPUOP_ARITH2_64_64(evfsadd); GEN_SPEFPUOP_ARITH2_64_64(evfssub); GEN_SPEFPUOP_ARITH2_64_64(evfsmul); GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); -static always_inline void gen_evfsabs (DisasContext *ctx) +static inline void gen_evfsabs(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7752,7 +7758,7 @@ static always_inline void gen_evfsabs (DisasContext *ctx) tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); #endif } -static always_inline void gen_evfsnabs (DisasContext *ctx) +static inline void gen_evfsnabs(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7765,7 +7771,7 @@ static always_inline void gen_evfsnabs (DisasContext *ctx) tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); #endif } -static always_inline void gen_evfsneg (DisasContext *ctx) +static inline void gen_evfsneg(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7821,7 +7827,7 @@ GEN_SPEFPUOP_ARITH2_32_32(efsadd); GEN_SPEFPUOP_ARITH2_32_32(efssub); GEN_SPEFPUOP_ARITH2_32_32(efsmul); GEN_SPEFPUOP_ARITH2_32_32(efsdiv); -static always_inline void gen_efsabs (DisasContext *ctx) +static inline void gen_efsabs(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7829,7 +7835,7 @@ static always_inline void gen_efsabs (DisasContext *ctx) } tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); } -static always_inline void gen_efsnabs (DisasContext *ctx) +static inline void gen_efsnabs(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7837,7 +7843,7 @@ static always_inline void gen_efsnabs (DisasContext *ctx) } tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); } -static always_inline void gen_efsneg (DisasContext *ctx) +static inline void gen_efsneg(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7889,7 +7895,7 @@ GEN_SPEFPUOP_ARITH2_64_64(efdadd); GEN_SPEFPUOP_ARITH2_64_64(efdsub); GEN_SPEFPUOP_ARITH2_64_64(efdmul); GEN_SPEFPUOP_ARITH2_64_64(efddiv); -static always_inline void gen_efdabs (DisasContext *ctx) +static inline void gen_efdabs(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7901,7 +7907,7 @@ static always_inline void gen_efdabs (DisasContext *ctx) tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); #endif } -static always_inline void gen_efdnabs (DisasContext *ctx) +static inline void gen_efdnabs(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -7913,7 +7919,7 @@ static always_inline void gen_efdnabs (DisasContext *ctx) tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); #endif } -static always_inline void gen_efdneg (DisasContext *ctx) +static inline void gen_efdneg(DisasContext *ctx) { if (unlikely(!ctx->spe_enabled)) { gen_exception(ctx, POWERPC_EXCP_APU); @@ -8936,9 +8942,9 @@ void cpu_dump_statistics (CPUState *env, FILE*f, } /*****************************************************************************/ -static always_inline void gen_intermediate_code_internal (CPUState *env, - TranslationBlock *tb, - int search_pc) +static inline void gen_intermediate_code_internal(CPUState *env, + TranslationBlock *tb, + int search_pc) { DisasContext ctx, *ctxp = &ctx; opc_handler_t **table, *handler; |