diff options
| -rw-r--r-- | target-alpha/helper.h | 4 | ||||
| -rw-r--r-- | target-alpha/op_helper.c | 20 | ||||
| -rw-r--r-- | target-alpha/translate.c | 45 |
3 files changed, 39 insertions, 30 deletions
diff --git a/target-alpha/helper.h b/target-alpha/helper.h index a5080770bf..6072a26b92 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -95,10 +95,6 @@ DEF_HELPER_FLAGS_1(cvttq, TCG_CALL_CONST, i64, i64) DEF_HELPER_FLAGS_1(cvttq_c, TCG_CALL_CONST, i64, i64) DEF_HELPER_FLAGS_1(cvttq_svic, TCG_CALL_CONST, i64, i64) -DEF_HELPER_FLAGS_1(cvtql, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64) -DEF_HELPER_1(cvtql_v, i64, i64) -DEF_HELPER_1(cvtql_sv, i64, i64) - DEF_HELPER_FLAGS_1(setroundmode, TCG_CALL_CONST, void, i32) DEF_HELPER_FLAGS_1(setflushzero, TCG_CALL_CONST, void, i32) DEF_HELPER_FLAGS_0(fp_exc_clear, TCG_CALL_CONST, void) diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 4d2c2ee58e..dd1af849c4 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1203,26 +1203,6 @@ uint64_t helper_cvtlq (uint64_t a) return (lo & 0x3FFFFFFF) | (hi & 0xc0000000); } -uint64_t helper_cvtql (uint64_t a) -{ - return ((a & 0xC0000000) << 32) | ((a & 0x7FFFFFFF) << 29); -} - -uint64_t helper_cvtql_v (uint64_t a) -{ - if ((int32_t)a != (int64_t)a) - helper_excp(EXCP_ARITH, EXC_M_IOV); - return helper_cvtql(a); -} - -uint64_t helper_cvtql_sv (uint64_t a) -{ - /* ??? I'm pretty sure there's nothing that /sv needs to do that /v - doesn't do. The only thing I can think is that /sv is a valid - instruction merely for completeness in the ISA. */ - return helper_cvtql_v(a); -} - /* PALcode support special instructions */ #if !defined (CONFIG_USER_ONLY) void helper_hw_rei (void) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 719b42319a..a4bf1fdf22 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -597,6 +597,41 @@ static inline void gen_fp_exc_raise(int rc, int fn11) gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact); } +static void gen_fcvtql(int rb, int rc) +{ + if (unlikely(rc == 31)) { + return; + } + if (unlikely(rb == 31)) { + tcg_gen_movi_i64(cpu_fir[rc], 0); + } else { + TCGv tmp = tcg_temp_new(); + + tcg_gen_andi_i64(tmp, cpu_fir[rb], 0xC0000000); + tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rb], 0x3FFFFFFF); + tcg_gen_shli_i64(tmp, tmp, 32); + tcg_gen_shli_i64(cpu_fir[rc], cpu_fir[rc], 29); + tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp); + + tcg_temp_free(tmp); + } +} + +static void gen_fcvtql_v(DisasContext *ctx, int rb, int rc) +{ + if (rb != 31) { + int lab = gen_new_label(); + TCGv tmp = tcg_temp_new(); + + tcg_gen_ext32s_i64(tmp, cpu_fir[rb]); + tcg_gen_brcond_i64(TCG_COND_EQ, tmp, cpu_fir[rb], lab); + gen_excp(ctx, EXCP_ARITH, EXC_M_IOV); + + gen_set_label(lab); + } + gen_fcvtql(rb, rc); +} + #define FARITH2(name) \ static inline void glue(gen_f, name)(int rb, int rc) \ { \ @@ -612,9 +647,6 @@ static inline void glue(gen_f, name)(int rb, int rc) \ } \ } FARITH2(cvtlq) -FARITH2(cvtql) -FARITH2(cvtql_v) -FARITH2(cvtql_sv) /* ??? VAX instruction qualifiers ignored. */ FARITH2(sqrtf) @@ -2244,11 +2276,12 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0x130: /* CVTQL/V */ - gen_fcvtql_v(rb, rc); - break; case 0x530: /* CVTQL/SV */ - gen_fcvtql_sv(rb, rc); + /* ??? I'm pretty sure there's nothing that /sv needs to do that + /v doesn't do. The only thing I can think is that /sv is a + valid instruction merely for completeness in the ISA. */ + gen_fcvtql_v(ctx, rb, rc); break; default: goto invalid_opc; |