diff options
| author | Anton Blanchard <anton@samba.org> | 2013-06-11 21:19:35 +1000 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-06-17 10:41:52 -0700 |
| commit | 8a94cfb05ea9a8991c832236b4174d354025a7b7 (patch) | |
| tree | 2d0a4602dbb5c02e55a21baa937d6152a8c11d41 /tcg | |
| parent | 38aea177d93556aada7c4c7aa530f0050715e293 (diff) | |
| download | qemu-8a94cfb05ea9a8991c832236b4174d354025a7b7.tar.gz qemu-8a94cfb05ea9a8991c832236b4174d354025a7b7.tar.bz2 qemu-8a94cfb05ea9a8991c832236b4174d354025a7b7.zip | |
tcg-ppc64: Fix RLDCL opcode
The rldcl instruction doesn't have an sh field, so the minor opcode
is shifted 1 bit. We were using the XO30 macro which shifted the
minor opcode 2 bits.
Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories.
Cc: qemu-stable@nongnu.org
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0fcf2b5daa..c7c0b8f94d 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -308,7 +308,8 @@ static int tcg_target_const_match (tcg_target_long val, #define OPCD(opc) ((opc)<<26) #define XO19(opc) (OPCD(19)|((opc)<<1)) -#define XO30(opc) (OPCD(30)|((opc)<<2)) +#define MD30(opc) (OPCD(30)|((opc)<<2)) +#define MDS30(opc) (OPCD(30)|((opc)<<1)) #define XO31(opc) (OPCD(31)|((opc)<<1)) #define XO58(opc) (OPCD(58)|(opc)) #define XO62(opc) (OPCD(62)|(opc)) @@ -354,10 +355,10 @@ static int tcg_target_const_match (tcg_target_long val, #define RLWINM OPCD( 21) #define RLWNM OPCD( 23) -#define RLDICL XO30( 0) -#define RLDICR XO30( 1) -#define RLDIMI XO30( 3) -#define RLDCL XO30( 8) +#define RLDICL MD30( 0) +#define RLDICR MD30( 1) +#define RLDIMI MD30( 3) +#define RLDCL MDS30( 8) #define BCLR XO19( 16) #define BCCTR XO19(528) |